Variable snubber for MOSFET application

Patent metadata

Field	Value
Publication number	US-10062685-B2
Application number	US-201715623210-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Mar 11, 2013
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

First claim

What is claimed is:

1. A transistor device, comprising:
one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a gate potential of the one or more gated structures during a switching event.

2. The device of claim 1 , wherein the one or more three-terminal resistors with the dynamically controllable resistance are formed above the gate electrode of one or more of the field effect transistor structures.

3. The device of claim 2 , wherein the one or more three-terminal resistors each include a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is the gate electrode of one or more of the field effect transistor structures.

4. The device of claim 1 , wherein the one or more three-terminal resistors with a dynamically controllable resistance are thin film transistors.

5. The device of claim 1 , wherein the one or more three-terminal resistors with a dynamically controllable resistance are metal-oxide-semiconductor field effect transistors (MOSFETs).

6. A transistor device, comprising:
one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a gate potential of the one or more gated structures during a switching event, wherein the one or more three-terminal resistors with a dynamically controllable resistance includes polysilicon disposed above the gate electrode of one or more of the field effect transistor structures.

7. The device of claim 6 , wherein the polysilicon disposed above the gate electrode is separated from the gate electrode by a dielectric layer.

8. The device of claim 7 , wherein each of the one or more gated structure comprises a trenche with the gate electrode formed therewithin.

9. The device of claim 8 , wherein each of the one or more gated structures further comprises a shield electrode inside the trench below the gate electrode.

10. The device of claim 6 , wherein the polysilicon disposed above the gate electrode comprises a source terminal and a drain terminal more heavily doped than a body region between the source terminal and the drain terminal.

11. A transistor device, comprising:
one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a drain potential of the one or more field effect transistor structures during a switching event.

12. The device of claim 11 , wherein the one or more three-terminal resistors with the dynamically controllable resistance are formed in a termination region of the transistor device, wherein the semiconductor substrate in the termination region is maintained at the drain potential of the one or more field effect transistor structures.

13. The device of claim 12 , wherein the one or more three-terminal resistors each include a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is the semiconductor substrate in the termination region that is maintained at the drain potential of the one or more field effect transistor structures.

14. The device of claim 12 , wherein the one or more three-terminal resistors with a dynamically controllable resistance are thin film transistor metal-oxide-semiconductor field effect transistors (TFT MOSFETs).

15. A transistor device, comprising:
one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a drain potential of the one or more field effect transistor structures during a switching event, wherein the one or more three-terminal resistors with a dynamically controllable resistance includes polysilicon disposed above the semiconductor substrate in a termination region of the transistor device, wherein the semiconductor substrate in the termination region is maintained at the drain potential of the one or more field effect transistor structures.

16. The device of claim 15 , wherein the polysilicon is disposed above a body type dopant region on a top portion of the semiconductor substrate in the termination region; wherein the body type dopant region is maintained at the drain potential of the one or more field effect transistor structures.

17. The device of claim 16 , wherein the polysilicon disposed above the body type dopant region is separated from the body type dopant region by a dielectric layer.

18. The device of claim 15 , wherein the polysilicon disposed above the gate electrode comprises a source terminal and a drain terminal more heavily doped than a body region between the source terminal and the drain terminal.

19. The device of claim 15 , wherein the one or more three-terminal resistors with a dynamically controllable resistance are metal-oxide-semiconductor field effect transistors (MOSFETs).

20. The device of claim 15 , wherein the one or more three-terminal resistors with a dynamically controllable resistance are junction field effect transistors (JFETs).

Assignees

• Alpha & Omega Semiconductor

Inventors

• Lui Sik
• Pan Ji

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H02M1/34 Primary

  Snubber circuits · CPC title

• H01L27/0629 Primary

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H02M2001/348

  Electricity · mapped topic