Power mosfet and manufacturing method thereof
US-2024322032-A1 · Sep 26, 2024 · US
Integrated MOSFET-Schottky diode device with reduced source and body Kelvin contact impedance and breakdown voltage
US8969950B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969950-B2 |
| Application number | US-201113306067-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 29, 2011 |
| Priority date | Dec 23, 2008 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.
First claim
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We claim: 1. An Integrated MOSFET-Schottky Diode semiconductor device, expressed in an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to its major semiconductor chip plane, comprising: a drain lying parallel to X-Y plane with an epitaxial layer overlaying the drain; a Kelvin-contact body disposed in the epitaxial layer with a Kelvin-contact source embedded in the Kelvin-contact body wherein the Kelvin-contact source conductivity type is opposite to that of the Kel…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8969950B2 cover?
- A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respec…
- Who is the assignee on this patent?
- Pan Ji, Alpha & Omega Semiconductor
- What technology area does this patent fall under?
- Primary CPC classification H10D30/668. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).