Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching

Patent metadata

Field	Value
Publication number	US-9006053-B2
Application number	US-201414264318-A
Country	US
Kind code	B2
Filing date	Apr 29, 2014
Priority date	Feb 11, 2005
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.

First claim

We claim:

1. A method for fabricating a MOSFET integrated with Schottky diode (MOSFET/SKY), expressed in an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to its major semiconductor chip plane, comprising:
a) forming, in an epitaxial layer overlaying a semiconductor substrate, a gate trench and depositing gate material therein;
b) forming a body region in the epitaxial layer, a source region atop the body region and a dielectric region atop the gate trench and the source region;
c) etching a top contact trench (TCT) with vertical side walls defining a X-Y cross sectional boundary for containing a Schottky diode there within, said X-Y cross sectional boundary
c1) going through the dielectric region and the source region thus defining a source-contact depth (SCD); and
c2) going partially into the body region by a predetermined total body-contact depth (TBCD);

d) creating:
d1) into the side walls of the TCT and beneath the SCD, a heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD; and
d2) into a sub-contact trench zone (SCTZ) beneath the floor of the TCT, an embedded Shannon implant region (ESIR); and

e) forming a metal layer:
e1) in contact with the ESIR, the body region and the source region; and
e2) filling the TCT and covering the dielectric region whereby completing the MOSFET/SKY with only one-time etching of its TCT.

2. The method of claim 1 wherein creating the heavily-doped EBIR and the ESIR comprising:
d11) implanting the heavily-doped EBIR while keeping the SCTZ essentially free of any concomitant body-contact implantation; and
d21) implanting the ESIR into the SCTZ.

3. The method of claim 2 wherein implanting the heavily-doped EBIR while keeping the SCTZ essentially free of any concomitant body-contact implantation comprising:
d111) forming a lower spacer sub-layer (LSSL) of horizontal wall thickness (HWT LS ) atop the side walls of the TCT and of vertical wall thickness (VWT LS ) atop the bottom floor of the TCT and atop the dielectric region with VWT LS essentially equal to HWT LS ;
d112) atop the LSSL, forming an upper spacer sub-layer (USSL) of horizontal wall thickness (HWT US ) atop the side walls of the TCT, of lower vertical wall thickness (LVWT US ) atop the bottom floor of the TCT and of upper vertical wall thickness (UVWT US ) atop the dielectric region with UVWT US essentially equal to HWT US but LVWT US >>HWT US ;
d113) selecting the LSSL material and the USSL material such that:
the LSSL would allow a through-transmission of a later body-implant beam while the USSL would, with a sufficiently large layer thickness, block a through-transmission of the later body-implant beam; and
the LSSL acts as an etch-stop for a later USSL-etching step;

d114) implanting, with the body-implant beam at a planetary body-implant tilt angle (BITA) with respect to the Z-axis and through a combined wall thickness of HWT US +HWT LS , the heavily-doped EBIR while, owing to the relationship LVWT US >>HWT US , keeping the SCTZ essentially free of any concomitant body-contact implantation whereby avoiding the otherwise concomitant body-contact implantation, into the SCTZ and bridging the EBIR, that would require an undesirable additional etching of the TCT to remove; and
d115) successively removing the USSL and the LSSL with an USSL-etching step and a LSSL-etching step.

4. The method of claim 3 wherein LVWT US >3*HWT US .

5. The method of claim 3 wherein:
the LSSL material is silicon nitride and the USSL material is high density plasma deposited silicon oxide (HDPSO);
VWT LS is from 100 to 500 Angstrom;
UVWT US is less than 0.1 micron while LVWT US is from 0.3 to 0.4 micron; and
The planetary BITA is from 15 to 30 degrees.

6. The method of claim 2 wherein implanting the ESIR into the SCTZ comprises implanting, with a Shannon-implant beam at a planetary Shannon-implant tilt angle (SITA) with respect to the Z-axis, the ESIR into the SCTZ.

7. The method of claim 6 wherein the planetary SITA is from about 7 degrees to about 15 degrees.

8. The method of claim 1 wherein forming the metal layer comprises depositing titanium/titanium nitride (Ti/TiN), forming a titanium silicide and filling the metal layer.

Assignees

• Alpha & Omega Semiconductor
• Alpha & Omega Semiconductor

Inventors

• Pan Ji
• Ng Daniel
• Tai Sung-Shan
• Bhalla Anup

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/21 Primary

  of electrically active species · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title