Generating a wafer inspection process using bit failures and virtual inspection

Patent metadata

Field	Value
Publication number	US-10014229-B2
Application number	US-201615041016-A
Country	US
Kind code	B2
Filing date	Feb 10, 2016
Priority date	Jan 18, 2012
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the water into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.

First claim

What is claimed is:

1. A system configured to generate a wafer inspection process, comprising:
an inspection subsystem configured to scan a wafer to detect defects on the wafer; and
one or more computer subsystems configured for:
storing output of one or more detectors of the inspection subsystem during the scanning regardless of whether the output corresponds to the defects detected on the wafer;
separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected;
storing information for the first portion of the physical locations as hot spots;
applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations, wherein said applying comprises iteratively applying the one or more defect detection methods to the stored output corresponding to the first portion of the physical locations, comparing the defects detected at the first portion of the physical locations to the bit failures, and changing one or more parameters of the one or more defect detection methods until the defects are detected at the first portion of the physical locations; and
generating a wafer inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations.

2. The system of claim 1 , wherein said separating comprises determining if the defects detected on the wafer correspond to any of the bit failures using locations of the bit failures and information about the physical locations of the defects detected on the wafer.

3. The system of claim 1 , wherein said separating is performed using bitmap domain coordinates.

4. The system of claim 1 , wherein said separating is performed using defect or wafer coordinates.

5. The system of claim 1 , wherein at least one of the one or more computer subsystems is further configured as a virtual inspector.

6. The system of claim 1 , wherein at least one of the one or more computer subsystems is further configured as a virtual inspector, and wherein the one or more computer subsystems are further configured for sending the hot spots to the virtual inspector.

7. The system of claim 1 , wherein the inspection subsystem or the one or more computer subsystems perform an inspection for the wafer by detecting the defects on the wafer using the output generated by the scanning, and wherein said applying further comprises performing a virtual inspection using the stored output to attempt to detect the defects that have caused the bit failures and were not detected during the inspection.

8. The system of claim 1 , wherein said applying does not comprise a layer inspection, and wherein said applying further comprises performing a number of discrete spot inspections at the first portion of the physical locations.

9. The system of claim 1 , wherein at least one of the one or more computer subsystems is further configured as a virtual inspector, and wherein the one or more computer subsystems are further configured for sending the bit failures corresponding to the first portion of the physical locations to the virtual inspector as the hot spots with physical coordinates corresponding to the physical locations in the first portion thereby using bitmap as the hot spots for the virtual inspector.

10. The system of claim 1 , wherein at least one of the one or more computer subsystems is further configured as a virtual inspector, and wherein the one or more computer subsystems are further configured for sending the bit failures corresponding to the first portion of the physical locations to the virtual inspector as the hot spots with physical coordinates corresponding to the physical locations in the first portion thereby using bitmap failures as one source of the hot spots for a virtual inspection performed by the virtual inspector.

11. The system of claim 1 , wherein storing the information comprises storing information for the first and second portions of the physical locations as the hot spots, and wherein said applying further comprises performing a number of discrete spot inspections at only the hot spots.

12. The system of claim 1 , wherein said applying further comprises fine tuning inspection parameters comprising the one or more parameters of the one or more defect detection methods on at least one of the one or more comp subsystems configured as a virtual inspector.

13. The system of claim 1 , wherein said applying further comprises performing a virtual inspection for the wafer at the first portion of the physical locations using the stored output, and wherein said generating comprises generating recipe parameters for the wafer inspection process based on one or more other defect detection methods used to detect the defects at the second portion of the physical locations and the one or more defect detection methods used to detect the defects at the first portion of the physical locations in the virtual inspection.

14. The system of claim 1 , wherein said applying further comprises performing a virtual inspection for the wafer, and wherein the one or more computer subsystems are further configured for sending the hot spots and the second portion of the physical locations at which the defects were detected to the virtual inspection.

15. The system of claim 1 , wherein said applying further comprises performing a virtual inspection for the wafer, and wherein the one or more computer subsystems are further configured for sending the second portion of the physical locations at which the defects were detected and are suspected to have caused the bit failures to the virtual inspection with the first portion of the physical locations at which the defects were not detected.

16. The system of claim 1 , wherein the inspection subsystem is further configured for bright field inspection of the wafer.

17. The system of claim 1 , wherein the inspection subsystem is further configured for dark field inspection of the wafer.

18. The system of claim 1 , wherein the inspection subsystem is further configured for bright field and dark field inspection.

19. The system of claim 1 , wherein the inspection subsystem is further configured for bright field and dark field inspection, and wherein the bright field and dark field inspection are performed sequentially.

20. The system of claim 1 , wherein the inspection subsystem is further configured for bright field and dark field inspection, and wherein the bright field and dark field inspection are performed simultaneously.

21. The system of claim 1 , wherein the wafer is not used for any step performed by the one or more computer subsystems.

22. The system of claim 1 , wherein the one or more computer subsystems are further configured for determining the physical locations on the wafer that correspond to the bit failures based on results of the testing.

23. The system of claim 1 , wherein the inspection subsystem comprises an optical or electron beam inspection subsystem.

24. The system of claim 1 , wherein the one or more computer subsystems are further configured for designating the defects detected by the one or more defect detection methods at the first portion of the physical locations as killer defects.

Assignees

• Kla Tencor Corp
• Kla Tencor Corp

Inventors

• Yong Poh Boon
• Simon George
• Du Yuezhong

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H04N7/18

  Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast · CPC title

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title