Method of fabricating package structure with an embedded electronic component

Patent metadata

Field	Value
Publication number	US-10002825-B2
Application number	US-201715625083-A
Country	US
Kind code	B2
Filing date	Jun 16, 2017
Priority date	Sep 12, 2014
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

First claim

What is claimed is:

1. A method of fabricating a package structure with an embedded component, comprising:
forming on a bonding carrier, a first wiring layer having opposing first and second surfaces, and disposing an electronic component on the bonding carrier, wherein the second surface of the first wiring layer is coupled to the bonding carrier;
forming on the first wiring layer an encapsulating layer that encapsulates the electronic component and is formed with at least a first hole for exposing a portion of the first surface of the first circuit therefrom;
removing the bonding carrier, wherein the electronic component is exposed from the encapsulating layer; and
forming a second wiring layer on the encapsulating layer, in a manner that a portion of the second wiring is filled into the at least a first hole, so as for the second wiring layer to be electrically connected with the first wiring layer.

2. The method of claim 1 , further comprising forming on the encapsulating layer a first insulating layer formed with at least a third hole, for exposing the portion of the second wiring layer exposed from the at least a first hole.

3. The method of claim 2 , wherein an end of the at least a first hole is flush with an end of the third hole.

4. The method of claim 1 , further comprising, after the second wiring layer is formed, forming a second insulating layer on the encapsulating layer on the second surface of the first wiring layer and on the first wiring layer.

5. The method of claim 4 , wherein the second insulating layer exposes a portion of the first wiring layer or the electronic component.

6. The method of claim 1 , further comprising, after, before or at the time the second wiring layer is formed, forming a plurality of connection pads on the second surface of the first wiring layer.

7. The method of claim 6 , further comprising forming a plurality of conductors on a chip, and then electrically connecting the chip to the connection pads and the electronic component through the conductors.

8. The method of claim 7 , wherein the conductors are solder bumps or copper pillars.

9. The method of claim 7 , further comprising forming a covering layer that covers the chip.

10. The method of claim 9 , wherein the chip has a top surface exposed from the covering layer.

11. The method of claim 1 , further comprising forming a plurality of conductors on a chip, and then coupling the chip to the first wiring layer and the electronic component through the conductors.

12. The method of claim 11 , wherein the conductors are solder bumps or copper pillars.

13. The method of claim 11 , further comprising forming a covering layer that covers the chip.

14. The method of claim 13 , wherein the chip has a top surface exposed from the covering layer.

15. The method of claim 1 , wherein forming the first wiring layer on the bonding carrier by comprises the steps of:
forming a seed layer on a carrier;
forming on the seed layer a patterned resist layer, from which a portion of the seed layer is exposed, such that the first wiring layer is formed on the exposed portion of the seed layer;
removing the patterned resist layer;
removing the carrier, and forming a second hole penetrating the seed layer;
coupling the bonding carrier to the seed layer, to carry the first wiring layer; and
coupling the electronic component to the bonding layer in the second hole.

16. The method of claim 15 , wherein the second hole penetrating the seed layer is formed before the carrier is removed.

17. The method of claim 15 , wherein the carrier is removed before the second hole penetrating the seed layer is formed.

18. The method of claim 15 , wherein the second hole is formed by etching, laser drilling, or mechanical drilling.

19. The method of claim 15 , wherein the carrier is a glass board or a metal board having an adhesive or a releasing agent on a surface thereof.

20. The method of claim 1 , wherein the encapsulating layer and the first hole are formed by applying a photosensitive material on the first surface of the first wiring layer, and performing an exposure and development process using a mask.

21. The method of claim 1 , wherein the encapsulating layer is formed by laminating or molding an epoxy resin on the first wiring layer, and using laser drilling method to form the first hole.

22. The method of claim 1 , wherein the electronic component is an active component or a passive component.

23. The method of claim 1 , wherein the bonding carrier is a tape.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chiu Shih-Chao
• Lin Chun-Hsien
• Pai Yu-Cheng
• Hsiao Wei-Chung
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/354

  comprising polymers · CPC title