Apparatus and method for intelligent memory page management
US-12579073-B2 · Mar 17, 2026 · US
This page is not indexed by search engines while we improve data quality.
Warnes Lidia patents
Warnes Lidia is listed as an inventor on 49 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Warnes Lidia |
| Total patents | 49 |
| First publication | Oct 15, 2015 |
| Latest publication | Mar 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory access tracing
US-12455821-B2 · Oct 28, 2025 · US
Method to minimize hot/cold page detection overhead on running workloads
US-12443537-B2 · Oct 14, 2025 · US
Memory pool management
US-12417121-B2 · Sep 16, 2025 · US
Memory thin provisioning using memory pools
US-12373335-B2 · Jul 29, 2025 · US
Ballooning for multi-tiered pooled memory
US-11983408-B2 · May 14, 2024 · US
Ballooning for multi-tiered pooled memory
US-2023333738-A1 · Oct 19, 2023 · US
Creating robustness scores for selected portions of a computing infrastructure
US-11693721-B2 · Jul 4, 2023 · US
Method and apparatus to perform workload management in a disaggregated computing system
US-2023195528-A1 · Jun 22, 2023 · US
Ballooning for multi-tiered pooled memory
US-11681439-B2 · Jun 20, 2023 · US
Recent patents
Latest publications not already listed above.
Method to minimize hot/cold page detection overhead on running workloads
US-2023092541-A1 · Mar 23, 2023 · US
Tenant based allocation for pooled memory
US-11573722-B2 · Feb 7, 2023 · US
Memory access tracing
US-2022334963-A1 · Oct 20, 2022 · US
Apparatus and method for intelligent memory page management
US-2022283951-A1 · Sep 8, 2022 · US
Memory pool management
US-2022050722-A1 · Feb 17, 2022 · US
Creating robustness scores for selected portions of a computing infrastructure
US-2022012112-A1 · Jan 13, 2022 · US
Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory
US-11074188-B2 · Jul 27, 2021 · US
Memory thin provisioning using memory pools
US-2021200667-A1 · Jul 1, 2021 · US
Error counters on a memory device
US-10891185-B2 · Jan 12, 2021 · US
Tenant based allocation for pooled memory
US-2020363975-A1 · Nov 19, 2020 · US
Ballooning for multi-tiered pooled memory
US-2020326861-A1 · Oct 15, 2020 · US
Validation of a repair to a selected row of data
US-10699796-B2 · Jun 30, 2020 · US
Partial backup during runtime for memory modules with volatile memory and non-volatile memory
US-10657003-B2 · May 19, 2020 · US
Handling errors during run time backups
US-10592364-B2 · Mar 17, 2020 · US
Status for generated data image
US-10481807-B2 · Nov 19, 2019 · US
Dynamically composable computing system, a data center, and method for dynamically composing a computing system
US-10402124-B2 · Sep 3, 2019 · US
Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory
US-2019179764-A1 · Jun 13, 2019 · US
Memory controller
US-10176043-B2 · Jan 8, 2019 · US
Dynamically composable computing system, a data center, and method for dynamically composing a computing system
US-2018284996-A1 · Oct 4, 2018 · US
Post package repair (PPR) data in non-volatile memory
US-10068661-B2 · Sep 4, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 23 |
| Hewlett Packard Entpr Dev Lp | 21 |
| Hewlett Packard Development Co | 4 |
| Hewlett Packard Development Co Lp | 2 |
| Warnes Lidia | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0604 | 9 |
| G06F3/0631 | 8 |
| G06F3/0673 | 8 |
| G06F11/106 | 7 |
| G06F2212/1024 | 6 |