Method to minimize hot/cold page detection overhead on running workloads

Patent metadata

Field	Value
Publication number	US-12443537-B2
Application number	US-202117483195-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Methods and apparatus to minimize hot/cold page detection overhead on running workloads. A page meta data structure is populated with meta data associated with memory pages in one or more far memory tier. In conjunction with one or more processes accessing memory pages to perform workloads, the page meta data structure is updated to reflect accesses to the memory pages. The page meta data is used to determine which pages are “hot” pages and which pages are “cold” pages, wherein hot pages are memory pages with relatively higher access frequencies and cold pages are memory pages with relatively lower access frequencies. Variations on the approach including filtering meta data updates on pages in memory regions of interest and applying a filter(s) to trigger meta data updates based on (a) condition(s). A callback function may also be triggered to be executed synchronously with memory page accesses.

First claim

What is claimed is:

1. A method implemented with a compute platform configured to access memory pages in a plurality of memory tiers including a near memory tier comprising local memory coupled to a processor in the compute platform and at least one far memory tier, comprising:
populating a page meta data structure with meta data associated with memory pages in the plurality of memory tiers;
in conjunction with one or more processes executing on the processor accessing memory pages, filtering, for each of at least one of the one or more processes, updating of page meta data for one or more selected memory pages accessed by that process, the filtering resulting in updating of page meta data for less than all the memory pages accessed by the process;
updating the page meta data structure to reflect accesses to memory pages including memory pages that are filtered; and
using the page meta data to determine which pages are hot pages and which pages are cold pages, wherein hot pages are memory pages with relatively higher access frequencies and cold pages are memory pages with relatively lower access frequencies.

2. The method of claim 1 , further comprising:
detecting a memory page in a far memory tier is a hot memory page;
detecting a memory page in the near memory tier is a cold memory page; and
copying the hot memory page into the near memory tier.

3. The method of claim 1 , wherein the page meta data structure is initially populated by performing operations comprising:
performing a page walk of memory pages in the far memory tier;
performing sampling of the memory pages as they are walked;
generating page meta data from the sampling; and
populating the page meta data structure with the page meta data that are generated.

4. The method of claim 1 , further comprising:
registering a hook in an operating system kernel to trigger a registered process associated with a kernel event comprising accessing a memory page; and
using the registered process to update page meta data for the page when the kernel event is triggered.

5. The method of claim 1 , further comprising:
enabling pages in one or more memory regions of interest to be defined for filtering; and
performing filtering on the page meta data updates, wherein page meta data are updated for memory page accesses to the pages defined for filtering, while page meta data are not updated for memory page accesses to pages that are not defined for filtering.

6. The method of claim 1 , further comprising:
registering a callback function to be called when an update is made to at least a portion of the page meta data in the page meta data structure; and
executing the callback function upon synchronous updates to the page meta data structure.

7. The method of claim 6 , further comprising implementing a filter on the callback function, the filter having a trigger based on a predetermined condition, wherein the callback function is called when the filter is triggered.

8. The method of claim 1 , wherein the plurality of memory tiers includes a far memory tier comprising memory that is accessed over a Compute Express Link (CXL) link or a flex-bus link.

9. The method of claim 1 , wherein the plurality of memory tiers includes a far memory tier comprising a remote memory pool.

10. A compute platform comprising:
a System on a Chip (SoC) including a central processing unit (CPU) having one or more cores on which software is executed including an operating system having a kernel and one or more processes associated with applications;
local memory coupled to the SoC comprising a near memory tier; and
at least one input-output (IO) interface configured to be coupled to memory in a far memory tier;
wherein execution of the software enables the compute platform to:
populate a page meta data structure with meta data associated with memory pages in the near memory tier and far memory tier;
in conjunction with one or more of the processes accessing memory pages in near and far memory tiers, filter, for each of at least one of the one or more processes, updating of page meta data for one or more selected memory pages accessed by that process, the filtering resulting in updating of page meta data for less than all the memory pages accessed by the process;
update the page meta data structure to reflect accesses to memory pages including memory pages that are filtered; and
employ the page meta data to determine which pages are hot pages and which pages are cold pages, wherein hot pages are memory pages with relatively higher access frequencies and cold pages are memory pages with relatively lower access frequencies.

11. The compute platform of claim 10 , wherein execution of the software further enables the compute platform to:
detect a memory page in a far memory tier is a hot memory page;
detecting a memory page in the near memory tier is a cold memory page; and
copy the hot memory page into the near memory tier.

12. The compute platform of claim 10 , wherein execution of the software further enables the compute platform to:
register a hook in the operating system kernel to trigger a registered process associated with a kernel event comprising accessing a memory page; and
use the registered process to update page meta for the memory page when the kernel event is triggered.

13. The compute platform of claim 10 , wherein execution of the software further enables the compute platform to:
enable pages in one or more memory regions of interest to be defined for filtering; and
perform filtering on the page meta data updates, wherein page meta data are updated for memory page accesses to the pages defined for filtering, while page meta data are not updated for memory page accesses to pages that are not defined for filtering.

14. The compute platform of claim 10 , wherein execution of the software further enables the compute platform to:
register a callback function to be called when an update is made to at least a portion of the page meta data in the page meta data structure; and
execute the callback function upon synchronous updates to the page meta data structure.

15. The compute platform of claim 10 , further comprising a Compute Express Link (CXL) interface or CXL controller coupled to a CXL memory card or at least one CXL Dual Inline Memory Module (DIMM).

16. A non-transitory machine-readable storage medium having instructions comprising an operating system including a kernel stored thereon, the operating system configured to be run on a compute platform via execution of the instructions on a processor of the compute platform, the processor coupled to local memory comprising near memory, the compute platform including or providing access to one or more tiers of far memory, wherein execution of the instructions enables the operating system to:
populate a page meta data structure with meta data associated with memory pages in the remote memory pool;
in conjunction with one or more processes executing on the processor accessing memory pages in a far memory tier, filter, for each of at least one of the one or more processes, updating of meta data for one or more selected memory pages in the far memory tier accessed by that process, the filtering resulting in updating of meta data for less than all the memory pages accessed by the process;
update the page meta data structure to reflect accesses to memory pages including memory pages that are filtered; and
employ the page meta data to determine which pages are hot pages and which pages are cold pages, wherein hot pages are memory pages with relatively higher access frequencies an

Assignees

• Intel Corp

Inventors

• Dugast Francois
• Srivastava Durgesh
• Sen Sujoy
• Warnes Lidia
• Willis Thomas E
• Coury Bassam N

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/123

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• G06F13/4208 Primary

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title