Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

Patent metadata

Field	Value
Publication number	US-11074188-B2
Application number	US-201916278509-A
Country	US
Kind code	B2
Filing date	Feb 18, 2019
Priority date	Feb 18, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

First claim

What is claimed is:

1. An apparatus comprising:
a two-level main memory, the two-level main memory comprising:
a persistent memory; and
a volatile memory, the persistent memory communicatively coupled to a persistent memory controller, the volatile memory communicatively coupled to a volatile memory controller, the volatile memory including:
a cache, the cache including a plurality of cache lines, each cache line to store a copy of data read from the persistent memory;
a dirty cache line tracker, the dirty cache line tracker to store a plurality of dirty cache line entries, each dirty cache line entry to store N dirty bits, each dirty bit corresponding to one of N consecutive cache lines in one of M consecutive rows in the cache, each row including N/M cache lines; and
a cache manager to read the N dirty bits in a dirty cache line entry to identify a location of a dirty cache line in the cache.

2. The apparatus of claim 1 , wherein the cache manager to write the dirty cache line associated with the dirty bit in the dirty cache line entry to the persistent memory.

3. The apparatus of claim 1 , wherein the cache manager to monitor a number of dirty lines in the dirty cache line tracker and to write dirty cache lines to the persistent memory while the number of dirty lines is greater than a threshold number of dirty lines.

4. The apparatus of claim 1 :
wherein the volatile memory controller including a dirty cache line tracker cache, the dirty cache line tracker cache to store a copy of dirty cache line entries stored in the dirty cache line tracker.

5. The apparatus of claim 4 , wherein the volatile memory controller to write data directly to a persistent memory address if cache is saturated and a dirty bit corresponding to a cache line associated with the persistent memory address indicates the cache line is clean.

6. The apparatus of claim 1 , wherein the persistent memory is a byte addressable write-in-place non-volatile memory.

7. The apparatus of claim 1 , wherein the volatile memory is a dynamic random access memory.

8. A method comprising:
storing in a cache, a copy of data read from a persistent memory in a two-level main memory, the two-level main memory comprising the persistent memory and a volatile memory comprising the cache, the persistent memory communicatively coupled to a persistent memory controller, the volatile memory communicatively coupled to a volatile memory controller, the cache including a plurality of cache lines, each cache line to store a copy of data read from the persistent memory;
storing a plurality of dirty cache line entries in a dirty cache line tracker, each dirty cache line entry to store N dirty bits, each dirty bit corresponding to one of N consecutive cache lines in one of M consecutive rows in the cache, each row including N/M cache lines; and
reading, by a cache manager, the N dirty bits in a dirty cache line entry to identify a location of a dirty cache line in the cache.

9. The method of claim 8 , wherein the cache manager to write the dirty cache line associated with the dirty bit in the dirty cache line entry to the persistent memory.

10. The method of claim 8 , wherein the cache manager to monitor a number of dirty lines in the dirty cache line tracker and to write dirty cache lines to the persistent memory while the number of dirty lines is greater than a threshold number of dirty lines.

11. The method of claim 8 , further comprising:
storing, by the volatile memory controller, a copy of dirty cache line entries stored in the dirty cache line tracker in a dirty cache line tracker cache in the volatile memory controller.

12. The method of claim 11 , further comprising:
writing, by the volatile memory controller, data directly to a persistent memory address if the cache is saturated and a dirty bit corresponding to a cache line associated with the persistent memory address indicates the cache line is clean.

13. The method of claim 11 , wherein the persistent memory is a byte addressable write-in-place non-volatile three dimensional cross point memory.

14. The method of claim 13 , wherein the volatile memory is a dynamic random access memory.

15. A system comprising:
a processor; and
a two-level main memory communicatively coupled to the processor, the two-level main memory comprising:
a persistent memory; and
a volatile memory, the persistent memory communicatively coupled to a persistent memory controller, the volatile memory communicatively coupled to a volatile memory controller, the volatile memory including:
a cache, the cache including a plurality of cache lines, each cache line to store a copy of data read from the persistent memory;
a dirty cache line tracker, the dirty cache line tracker to store a plurality of dirty cache line entries, each dirty cache line entry to store N dirty bits, each dirty bit corresponding to one of N consecutive cache lines in one of M consecutive rows in the cache, each row including N/M cache lines; and
a cache manager to read the N dirty bits in a dirty cache line entry to identify a location of a dirty cache line in the cache.

16. The system of claim 15 , wherein the cache manager to write the dirty cache line associated with the dirty bit in the dirty cache line entry to the persistent memory.

17. The system of claim 15 , wherein the cache manager to monitor a number of dirty lines in the dirty cache line tracker and to write dirty cache lines to the persistent memory while the number of dirty lines is greater than a threshold number of dirty lines.

18. The system of claim 15 :
wherein the volatile memory controller including a dirty cache line tracker cache, the dirty cache line tracker cache to store a copy of dirty cache line entries stored in the dirty cache line tracker.

19. The system of claim 18 , wherein the volatile memory controller to write data directly to a persistent memory address if cache is saturated and a dirty bit corresponding to a cache line associated with the persistent memory address indicates the cache line is clean.

20. The system of claim 15 , wherein the persistent memory is a byte addressable write-in-place non-volatile memory.

Assignees

• Intel Corp

Inventors

• Wang Zhe
• Alameldeen Alaa R
• Warnes Lidia
• Rudoff Andy M
• Swaminathan Muthukumar P

Classifications

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F12/0893

  Caches characterised by their organisation or structure · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F12/0877 Primary

  Cache access modes · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title