Validation of a repair to a selected row of data

Patent metadata

Field	Value
Publication number	US-10699796-B2
Application number	US-201415310629-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	May 27, 2014
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.

First claim

What is claimed is:

1. A digital circuit comprising:
a control register configured to:
enable a first data path that initiates a validation of a repair to a selected row of data among multiple rows of data of a memory array;
enable a second data path that represents a state of the selected row of data prior to the repair; and
enable a third data path that represents the repair to the selected row of data; and

a logic component configured to determine if the repair to the selected row of data is successful; and
a controller configured to in response to the determination that the validation of the repair to the selected row of data was unsuccessful, revert the selected row of data back to the state prior to the repair; and a fusible link, within the first data path, configured to enable the validation of the repair to the selected row of data, wherein each row of data corresponds to a different fusible link.

2. The digital circuit of claim 1 further comprising:
a data register configured to identify the selected row of data among the multiple rows of data; and
the logic component configured to validate the repair to the identified selected row of data.

3. The digital circuit of claim 1 wherein the selected row of data is a dynamic random-access memory (DRAM) and each row of data includes a different bit of data.

4. The digital circuit of claim 1 wherein in response that the repair to the selected row of data was unsuccessful, the controller is further configured to:
select another row of data, among the multiple rows of data, that enables three different data paths to validate a repair made to the selected another row of data.

5. The digital circuit of claim 1 wherein the logic component is further to:
in response to the determination that the validation of the repair to the selected row of data was successful, permanently store the state of the repair to the selected row of data.

6. A non-transitory machine-readable storage medium comprising instructions that when executed by a processor cause the processor to:
select a row of data, among multiple rows of data of a memory array, that includes a temporary repair;
in response to a determination that the temporary repair was successful, validate the temporary repair to the selected row of data such that the temporary repair becomes a permanent repair;
in response to the determination that the temporary repair to the selected row of data was unsuccessful, revert the selected row of data back to a state prior to the temporary repair; and enable a first data path that opens a fusible link to initiate the validation of the temporary repair to the selected row of data; enable a second data path that represents the selected row of data prior to the temporary repair; and enable a third data path that represents the repair to the selected row; and determine that the temporary repair to the selected row of data was successful.

7. The non-transitory machine-readable storage medium including the instructions of claim 6 wherein in response to the determination that the temporary repair to the selected row of data was unsuccessful comprises instructions that when executed by the processor cause the processor to:
select another row of data among the multiple rows of data to validate a different repair made to the selected another row of data.

8. The non-transitory machine-readable storage medium including the instructions of claim 6 wherein in response to the determination that the temporary repair was successful, validate the temporary repair to the selected row of data such that the temporary repair becomes the permanent repair comprises instructions that when executed by the processor cause the processor to:
write the temporary repair to the selected row of data.

9. The method of claim 6 wherein the multiple rows of data are isolated from one another.

10. A method, executable by a computing device, the method comprising:
selecting a row of data, among multiple rows of data of a memory array, that includes a temporary repair made to the selected row of data;
validating the temporary repair made to the selected row of data by a determination of whether the temporary repair was successful or unsuccessful;
in response to a determination that the temporary pair was successful, writing the temporary repair to the selected row of data such that the temporary repair becomes a permanent repair; and
in response to the determination that the temporary repair to the selected row of data was unsuccessful, reverting the selected row of data back to a state prior to the temporary repair; and enabling a first data path that opens a fusible link to initiate the validation of the temporary repair made to the selected row of data; enabling a second data path that represents the selected row of data prior to the temporary repair; and enabling a third data path that represents the repair made to the selected row of data.

11. The method of claim 10 wherein in response to the determination that the temporary repair was unsuccessful, the method comprises:
selecting another row of data, among the multiple rows of data, that includes a different temporary repair made to the selected another row of data.

12. The method of claim 10 wherein selecting the row of data, among multiple rows of data, to validate the temporary repair occurs post-repair.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Benedict Melvin K
• Pope Eric L
• Warnes Lidia

Classifications

• G11C29/24 Primary

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title