Memory pool management

Patent metadata

Field	Value
Publication number	US-12417121-B2
Application number	US-202117514530-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Oct 29, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Examples described herein relate to providing an interface to an operating system (OS) to create different memory pool classes to allocate to one or more processes and allocate a memory pool class with a process of the one or more processes. In some examples, a memory pool class of the different memory pool classes defines a mixture of memory devices in at least one memory pool available for access by the one or more processes. In some examples, memory devices are associated with multiple memory pool classes to provide multiple different categories of memory resource capabilities.

First claim

What is claimed is:

1. At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
provide an interface to an operating system (OS) to create different memory pool classes to allocate to one or more processes and
allocate a memory pool class with a process of the one or more processes, wherein based on migration of the process of the one or more processes to execute on another compute node, the migrated process retains access to the allocated memory pool class.

2. The computer-readable medium of claim 1 , wherein the interface comprises an application programming interface (API) or configuration file.

3. The computer-readable medium of claim 1 , wherein a memory pool class of the different memory pool classes defines a mixture of memory devices in at least one memory pool available for access by the one or more processes.

4. The computer-readable medium of claim 1 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
associate memory devices with multiple memory pool classes to provide multiple different categories of memory resource capabilities.

5. The computer-readable medium of claim 1 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
change memory devices associated with the memory pool class of the different memory pool classes based on changes in memory resource availability.

6. The computer-readable medium of claim 1 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
associate the memory pool class with a service level agreement (SLA) class, wherein the SLA class specifies required memory resource capabilities of the process of the one or more processes.

7. The computer-readable medium of claim 1 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
classify a group of two or more memory pages into a cluster based on number of accesses over a time period;
classify a second group of two or more memory pages into a second cluster based on number of accesses over the time period; and
on a cluster-by-cluster basis, determine whether to pre-fetch data or migrate data associated with the cluster.

8. The computer-readable medium of claim 7 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
provide page access numbers over a time region to identify accesses of a page over time.

9. The computer-readable medium of claim 7 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
predict whether data associated with the cluster is to be accessed in a future time period, wherein the determine whether to pre-fetch data or migrate data associated with the cluster comprises:
based on a prediction that data associated with the cluster is to be accessed in the future time period, pre-fetch the data into a memory that is associated with lower latency access than a memory that stores the data.

10. The computer-readable medium of claim 9 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
based on a prediction that data associated with the cluster is not to be accessed in the future time period, migrate the data into a memory that is associated with higher latency access than a memory that stores the data.

11. The computer-readable medium of claim 9 , wherein the pre-fetch the data into a memory that is associated with lower latency access than a memory that stores the data comprises:
cause data migration when memory bandwidth occupation is anticipated to be less than a level.

12. The computer-readable medium of claim 1 , wherein the another compute node comprises a processor and wherein the processor comprises one or more of: a central processing unit (CPU), graphics processing unit (GPU), core, field programmable gate array (FPGA), application specific integrated circuit (ASIC), and/or memory device.

13. An apparatus comprising:
a processor to execute an orchestrator and
a memory pool comprising memory devices and circuitry, when operational, configured to:
provide access to a set of one or more memory devices in the memory pool in connection with an access to a memory pool class, wherein the set of one or more memory devices in the memory pool are allocated to the memory pool class and wherein the orchestrator is to select a server to execute a process based on capability of the server to access the set of one or memory devices associated with the memory pool class meeting or exceeding a service level agreement (SLA) associated with the process.

14. The apparatus of claim 13 , wherein the memory pool class is to define a mixture of memory devices in the memory pool available for access by one or more processes.

15. The apparatus of claim 13 , wherein a second set of one or more memory devices in the memory pool are allocated to a second memory pool class and wherein the set and second set of one or more memory devices are associated with different categories of memory resource capabilities.

16. The apparatus of claim 13 , comprising a server communicatively coupled to the memory pool, wherein a process is allocated to access the set of one or more memory devices associated with the memory pool class and wherein based on migration of the process from the server to the another server, the migrated process is to retain access to the set of one or more memory devices.

17. The apparatus of claim 13 , comprising a server communicatively coupled to the memory pool and comprising a memory device, wherein the memory device is allocated to the memory pool class.

18. The apparatus of claim 13 , comprising a server communicatively coupled to the memory pool, wherein the server is to:
provide an interface to an operating system (OS) to create different memory pool classes to allocate to one or more processes executed on the server and
allocate the memory pool class to a process of the one or more processes.

19. A method comprising:
allocating one of different memory pool classes to a process, wherein the allocated memory pool class is associated with a mixture of memory devices comprising memory devices of a memory pool;
classifying a group of two or more memory pages into a cluster based on number of accesses over a time period;
classifying a second group of two or more memory pages into a second cluster based on a number of accesses over the time period; and
on a cluster-by-cluster basis, determining whether to pre-fetch data or migrate data associated with the cluster.

20. The method of claim 19 , comprising:
selecting a processor to execute a process based on capability of the processor to access the memory devices of the memory pool.

21. The method of claim 19 , comprising:
providing access to a set of one or more memory devices in the memory pool in connection with an access to a memory pool class, wherein the set of one or more memory devices in the memory pool are allocated to the memory pool class and
selecting a processor to execute the process based on capability of the processor to access the set of one or memory devices associated with the memory pool class meeting or exceeding

Assignees

• Intel Corp

Inventors

• Dugast Francois
• Pirou Florent
• Sen Sujoy
• Warnes Lidia
• Willis Thomas E
• Srivastava Durgesh

Classifications

• G06F9/505

  considering the load · CPC title

• G06F9/4406

  Loading of operating system · CPC title

• G06F9/541

  via adapters, e.g. between incompatible applications · CPC title

• G06F2209/5011

  Pool · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title