Bipolar junction transistor
US-2023352570-A1 · Nov 2, 2023 · US
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Stephens Jason E patents
Stephens Jason E is listed as an inventor on 29 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Stephens Jason E |
| Total patents | 29 |
| First publication | Jul 30, 2015 |
| Latest publication | Nov 2, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Middle of the line self-aligned direct pattern contacts
US-11043418-B2 · Jun 22, 2021 · US
Merge mandrel features
US-10741439-B2 · Aug 11, 2020 · US
Middle of the line self-aligned direct pattern contacts
US-2020083102-A1 · Mar 12, 2020 · US
Middle of the line self-aligned direct pattern contacts
US-10522403-B2 · Dec 31, 2019 · US
Merge mandrel features
US-2019267281-A1 · Aug 29, 2019 · US
Merge mandrel features
US-2019221474-A1 · Jul 18, 2019 · US
Middle of the line self-aligned direct pattern contacts
US-2019214298-A1 · Jul 11, 2019 · US
Merge mandrel features
US-10340180-B1 · Jul 2, 2019 · US
Methods of forming conductive lines and vias and the resulting structures
US-2019139823-A1 · May 9, 2019 · US
Recent patents
Latest publications not already listed above.
Transistor contacts self-aligned in two dimensions
US-10056373-B2 · Aug 21, 2018 · US
Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices
US-9825031-B1 · Nov 21, 2017 · US
Transistor contacts self-aligned in two dimensions
US-2017221886-A1 · Aug 3, 2017 · US
Transistor contacts self-aligned two dimensions
US-9660040-B2 · May 23, 2017 · US
Borderless contact formation through metal-recess dual cap integration
US-9502528-B2 · Nov 22, 2016 · US
Methods of cross-coupling line segments on a wafer
US-9472455-B2 · Oct 18, 2016 · US
Method for creating self-aligned transistor contacts
US-9461128-B2 · Oct 4, 2016 · US
Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines
US-9412655-B1 · Aug 9, 2016 · US
Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines
US-2016225666-A1 · Aug 4, 2016 · US
Method for creating self-aligned transistor contacts
US-2016093704-A1 · Mar 31, 2016 · US
Borderless contact formation through metal-recess dual cap integration
US-2016064514-A1 · Mar 3, 2016 · US
Transistor contacts self-aligned two dimensions
US-2016049481-A1 · Feb 18, 2016 · US
Method for creating self-aligned transistor contacts
US-9236437-B2 · Jan 12, 2016 · US
Forming cross-coupled line segments
US-9224617-B2 · Dec 29, 2015 · US
Transistor contacts self-aligned in two dimensions
US-9202751-B2 · Dec 1, 2015 · US
Methods of cross-coupling line segments on a wafer
US-2015287604-A1 · Oct 8, 2015 · US
Transistor contacts self-aligned in two dimensions
US-2015287636-A1 · Oct 8, 2015 · US
Method for creating self-aligned transistor contacts
US-2015236106-A1 · Aug 20, 2015 · US
Forming cross-coupled line segments
US-2015214064-A1 · Jul 30, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Globalfoundries Inc | 27 |
| Globalfoundries Us Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/069 | 19 |
| H10D84/038 | 17 |
| H10W20/0698 | 17 |
| H10W20/077 | 14 |
| H10D84/0186 | 12 |