Method for creating self-aligned transistor contacts

Patent metadata

Field	Value
Publication number	US-9236437-B2
Application number	US-201414184830-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Feb 20, 2014
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming a plurality of gates in a dielectric layer;
recessing the plurality of gates;
depositing a capping layer over the plurality of gates;
forming a first mask layer having a patterned opening therein;
performing a selective dielectric etch within the patterned opening to form a plurality of source/drain (S/D) cavities;
depositing a source/drain contact metal in the S/D cavities to form a plurality of contact strips;
forming a second mask layer comprising a plurality of regions disposed over a portion of the capping layer and a portion of an adjacent contact strip of the plurality of contact strips;
performing an etch of the adjacent contact strip to form a source/drain contact.

2. The method of claim 1 , further comprising:
forming a third mask layer having a patterned opening therein, wherein the patterned opening in the third mask layer is disposed above one of the plurality of gates;
performing an etch of the capping layer;
forming an opening in the gate; and
depositing a second capping layer in the opening in the gate.

3. The method of claim 1 , wherein depositing a capping layer comprises depositing a layer comprised of silicon nitride.

4. The method of claim 3 , further comprising planarizing the capping layer flush with the dielectric layer.

5. The method of claim 1 , further comprising planarizing the source/drain contact metal flush with the dielectric layer.

6. The method of claim 5 , wherein planarizing the source/drain contact metal is performed using a chemical mechanical polish process.

7. The method of claim 2 , wherein forming gates comprises depositing tungsten.

8. The method of claim 7 , wherein depositing a source/drain contact metal comprises depositing a material selected from the group consisting of cobalt, tungsten, and copper.

Assignees

• Globalfoundries Inc

Inventors

• Zaleski Mark A
• Wei Andy Chih-Hung
• Stephens Jason E
• Neogi Tuhin Guha
• Bouche Guillaume

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title