Metal-free frame design for silicon bridges for semiconductor packages

Patent metadata

Field	Value
Publication number	US-12074121-B2
Application number	US-202318128954-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Oct 29, 2015
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having an insulating layer thereon, the substrate comprising silicon;
a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;
a first metal ring in the dielectric material stack and continuous around the conductive routing, wherein the first metal ring comprises a vertical stack of alternating metal lines and vias, the alternating metal lines comprising a first metal line, a second metal line above the first metal line, a third metal line above the second metal line, and a fourth metal line above the third metal line;
a second metal ring in the dielectric material stack and continuous around the first metal ring; and
a plurality of staggered non-continuous metal rings adjacent to the second metal ring.

2. The semiconductor structure of claim 1 , wherein the plurality of staggered non-continuous metal rings is between the second metal ring and the first metal ring.

3. The semiconductor structure of claim 1 , wherein at least one of the first metal ring or the second metal ring provides a hermetic seal for the metallization structure.

4. The semiconductor structure of claim 1 , further comprising:
a metal feature between the first metal ring and the second metal ring, the metal feature selected from the group consisting of an alignment mark, a dummy feature, and a test feature.

5. The semiconductor structure of claim 1 , wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon.

6. The semiconductor structure of claim 5 , wherein the conductive routing electrically couples the first plurality of conductive pads with the second plurality of conductive pads.

7. The semiconductor structure of claim 5 , wherein the first and second pluralities of conductive pads comprise a layer of copper having a thickness of greater than approximately 5 microns.

8. The semiconductor structure of claim 1 , wherein the substrate is free from having semiconductor devices therein.

9. The semiconductor structure of claim 1 , wherein the substrate is a single crystalline silicon substrate.

10. A semiconductor structure, comprising:
a substrate having an insulating layer thereon, the substrate comprising silicon;
a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;
a first metal ring in the dielectric material stack and adjacent to the conductive routing of the metallization structure, wherein the first metal ring comprises a first metal line, a first metal via above the first metal line, a second metal line above the first metal via, a second metal via above the second metal line, a third metal line above the second metal via, a third metal via above the third metal line, and a fourth metal line above the third metal via;
a second metal ring in the dielectric material stack and adjacent to the first metal ring; and
a plurality of staggered dummy metal features adjacent to the second metal ring.

11. The semiconductor structure of claim 10 , wherein the first metal ring is continuous around the conductive routing of the metallization structure.

12. The semiconductor structure of claim 10 , wherein the second metal ring is continuous around the first metal ring.

13. The semiconductor structure of claim 10 , wherein the first metal ring is continuous around the conductive routing of the metallization structure, and wherein the second metal ring is continuous around the first metal ring.

14. The semiconductor structure of claim 10 , wherein the plurality of staggered dummy metal features is between the second metal ring and the first metal ring.

15. A semiconductor structure, comprising:
a substrate having an insulating layer thereon, the substrate comprising silicon;
a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;
a first metal guard ring in the dielectric material stack and continuous around the conductive routing;
a second metal guard ring in the dielectric material stack and continuous around the first metal guard ring; and
a plurality of staggered mini guard rings adjacent to the second metal ring.

16. The semiconductor structure of claim 15 , wherein the plurality of staggered mini guard rings is between the second metal guard ring and the first metal guard ring.

17. The semiconductor structure of claim 15 , wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon, and wherein the conductive routing electrically couples the first plurality of conductive pads with the second plurality of conductive pads.

18. The semiconductor structure of claim 17 , wherein the first and second pluralities of conductive pads comprise a layer of copper having a thickness of greater than approximately 5 microns.

19. The semiconductor structure of claim 15 , wherein the substrate is free from having semiconductor devices therein.

20. The semiconductor structure of claim 15 , wherein the substrate is a single crystalline silicon substrate.

Assignees

• Intel Corp

Inventors

• Kim Dae-Woo
• Sharan Sujit
• Agraharam Sairam

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title