Substrateless double-sided embedded multi-die interconnect bridge

Patent metadata

Field	Value
Publication number	US-12341129-B2
Application number	US-201916440218-A
Country	US
Kind code	B2
Filing date	Jun 13, 2019
Priority date	Jun 13, 2019
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a substrate having a conductive plane at an outermost surface of the substrate;
a first die;
a second die; and
a bridge, embedded in the substrate above the conductive plane of the substrate, wherein the conductive plane is continuous along an entire width of the bridge, the bridge having first contacts at a first surface of the bridge and second contacts at an opposing second surface of the bridge, the first surface below the second surface, the bridge comprising:
a first conductive pathway coupling the first die to the second die; a second conductive pathway coupling the first die to the second die, the second conductive pathway below the first conductive pathway; and
a plurality of vias arranged vertically and coupled to the second conductive pathway, the plurality of vias below the second conductive pathway, wherein each via of the plurality of vias vertically overlaps with an individual first contact of the first contacts, wherein an individual via of the plurality of vias is coupled to the individual first contact, wherein the individual first contact is coupled to the conductive plane in the substrate, and wherein the first die and the second die are coupled to one or more of the second contacts at the second surface of the bridge.

2. The microelectronic assembly of claim 1 , wherein the bridge further includes:
a conductive plane between the plurality of vias and coupled to the plurality of vias.

3. The microelectronic assembly of claim 2 , wherein the conductive plane in the bridge is a first conductive plane, and wherein the bridge further includes: a second conductive plane; and a capacitor between the first conductive plane and the second conductive plane.

4. The microelectronic assembly of claim 3 , wherein the capacitor is a metal-insulator-metal (MIM) capacitor.

5. The microelectronic assembly of claim 1 , wherein the bridge does not include a silicon substrate.

6. The microelectronic assembly of claim 1 , wherein the bridge includes one or more of silicon dioxide, silicon nitride, oxynitride, organo-silicate glass (OSG), and silicon oxycarbide (SiOC).

7. The microelectronic assembly of claim 1 , wherein the individual first contact is coupled to the conductive plane in the substrate by a conductive pillar or a solder joint.

8. The microelectronic assembly of claim 1 , wherein the one or more second contacts are coupled to the first die by solder or a conductive pillar.

9. A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package disposed on the circuit board, wherein the IC package includes:
a package substrate having a conductive plane at an outermost surface of the substrate;
a bridge above the conductive plane of the package substrate, wherein the conductive plane is continuous along an entire width of the bridge, the bridge having a plurality of first contacts at a first surface of the bridge, the first surface below the second surface, a plurality of second contacts at an opposing second surface of the bridge, and a conductive pathway above a plurality of vertically stacked vias and coupling a first die and a second die, the conductive pathway and the plurality of vertically stacked vias between an individual first contact of the plurality of first contacts and an individual contact second contact of the plurality of second contacts, wherein each via of the plurality of vertically stacked vias vertically overlaps with the individual first contact, wherein the bridge is embedded in the package substrate and coupled to the conductive plane in the package substrate via the individual first contact; and
one of the first die and the second die is coupled to the individual second contact at the second surface of the bridge and coupled to the conductive plane in the package substrate by the plurality of vertically stacked vias.

10. The computing device of claim 9 , wherein the conductive pathway is a first conductive pathway, and the computing device further comprises:
the other of the first die and the second die is coupled to the second surface of the bridge by another second contact of the plurality of second contacts and coupled to the first die by a second conductive pathway in the bridge.

11. The computing device of claim 9 , wherein the bridge does not include a silicon substrate.

12. The computing device of claim 9 , wherein the bridge includes one or more of silicon dioxide, silicon nitride, oxynitride, organo-silicate glass (OSG), and silicon oxycarbide (SiOC).

13. The computing device of claim 9 , wherein the conductive plane in the package substrate is coupled to a power source.

14. The computing device of claim 9 , wherein the conductive plane in the package substrate is coupled to a ground source.

15. The computing device of claim 9 , wherein the computing device is a wearable computing device.

16. An integrated circuit (IC) package, comprising:
a package substrate having a conductive plane at an outermost surface of the substrate;
a first die;
a second die; and
a bridge above the conductive plane of the package substrate, wherein the conductive plane is continuous along an entire width of the bridge, the bridge having first contacts on a first surface of the bridge and second contacts on an opposing second surface of the bridge, the first surface below the second surface, wherein the bridge is embedded in the package substrate, wherein the bridge is coupled to the conductive plane in the package substrate via the first contacts, wherein the first die and the second die are coupled to the bridge via the second contacts, wherein the bridge does not include a silicon substrate, and wherein the bridge includes:
a first conductive pathway coupling the first die to the second die; and
a second conductive pathway coupled to a conductive plane in the bridge, the second conductive pathway below the first conductive pathway, wherein the second conductive pathway is above a plurality of vertically stacked conductive vias, wherein the plurality of vertically stacked conductive vias vertically overlaps with the individual first contact.

17. The IC package of claim 16 , wherein the bridge is a first bridge, and the IC package further comprises: a second bridge having third contacts on a first surface of the second bridge and fourth contacts on an opposing second surface of the second bridge, wherein the second bridge is embedded in the package substrate beneath the first bridge, wherein the second bridge is coupled to the conductive plane in the package substrate via the third contacts, and wherein the second bridge includes the plurality of vertically stacked conductive vias between an individual third contact of the third contacts and an individual fourth contact of the fourth contacts, and wherein the individual fourth contact is coupled to the individual first contact.

18. The IC package of claim 17 , wherein the second bridge further comprises: a conductive plane between the plurality of vertically stacked conductive vias.

19. The IC package of claim 17 , wherein the first bridge is coupled to the second bridge by solder.

20. The IC package of claim 17 , wherein the first bridge is coupled to the second bridge by a conductive adhesive.

Assignees

• Intel Corp

Inventors

• Xie Biancun
• Xie Jianyong
• Sharan Sujit
• Mallik Debendra
• Sankman Robert L

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title