Capacitor die embedded in package substrate for providing capacitance to surface mounted die

Patent metadata

Field	Value
Publication number	US-12046568-B2
Application number	US-202318214742-A
Country	US
Kind code	B2
Filing date	Jun 27, 2023
Priority date	Mar 30, 2018
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

First claim

What is claimed is:

1. A package, comprising:
a die;
a surface mount die laterally spaced apart from the die, the surface mount die having a footprint;
a bridge die below the die and the surface mount die, the bridge die coupled to the die, and the bridge die coupled to the surface mount die, wherein the bridge die is partially within the footprint of the surface mount die;
a first capacitor die below the surface mount die, the first capacitor die entirely within the footprint of the surface mount die, wherein the first capacitor die is a first silicon-based capacitor die and is a first single-sided capacitor die; and
a second capacitor die below the surface mount die, the second capacitor die entirely within the footprint of the surface mount die, wherein the second capacitor die is a second silicon-based capacitor die and is a second single-sided capacitor die.

2. The package of claim 1 , wherein the second capacitor die is laterally spaced apart from the first capacitor die.

3. The package of claim 2 , wherein the bridge die is laterally spaced apart from the first capacitor die.

4. The package of claim 1 , further comprising:
a third capacitor die below the surface mount die, the third capacitor die entirely within the footprint of the surface mount die, wherein the third capacitor die is a third silicon-based capacitor die and is a third single-sided capacitor die.

5. The package of claim 1 , further comprising:
a second die laterally spaced apart from the surface mount die, the second die on a side of the surface mount die laterally opposite the die.

6. The package of claim 5 , further comprising:
a second bridge die below the second die and the surface mount die, the second bridge die coupled to the second die, and the second bridge die coupled to the surface mount die.

7. The package of claim 1 , wherein the bridge die is an embedded interconnect bridge (EMIB) die.

8. The package of claim 1 , wherein the bridge die is partially within a footprint of the die.

9. The package of claim 1 , wherein the die is a processor die.

10. A package, comprising:
a first die having a footprint;
a second die laterally spaced apart from the first die, the second die having a footprint;
a third die below the first die and the second die, the third die coupled to the first die, and the third die coupled to the second die, wherein the third die is partially within the footprint of the first die and is partially within the footprint of the second die;
a first capacitor die below the second die, the first capacitor die entirely within the footprint of the second die;
a second capacitor die below the second die, the second capacitor die entirely within the footprint of the second die, and the second capacitor die laterally spaced apart from the first capacitor die; and
a third capacitor die below the second die, the third capacitor die entirely within the footprint of the second die, and the third capacitor die laterally spaced apart from the second capacitor die.

11. The package of claim 10 , wherein each of the first capacitor die, the second capacitor die, and the third capacitor die has connections on only a single side of the capacitor die.

12. The package of claim 10 , wherein each of the first capacitor die, the second capacitor die, and the third capacitor die has connections on both sides of the capacitor die.

13. The package of claim 10 , wherein each of the first capacitor die, the second capacitor die, and the third capacitor die is a silicon-based capacitor die.

14. The package of claim 10 , wherein the third die is laterally spaced apart from the first capacitor die.

15. The package of claim 10 , further comprising:
a fourth die laterally spaced apart from the second die, the fourth die on a side of the second die laterally opposite the first die.

16. The package of claim 10 , wherein the first die is a processor die, and the third die is an embedded interconnect bridge (EMIB) die.

17. A package, comprising:
a surface mount die having a footprint, the surface mount die having a first side and a second side, the second side laterally opposite the first side;
a first die laterally spaced apart from the first side of the first die surface mount die, the first die having a footprint;
a second die laterally spaced apart from the first die;
a third die laterally spaced apart from the second side of the surface mount die;
a fourth die laterally spaced apart from the third die;
a bridge die below the first die and the surface mount die, the bridge die coupled to the first die, and the bridge die coupled to the surface mount die, wherein the bridge die is partially within the footprint of the surface mount die and is partially within the footprint of the first die;
a first capacitor die below the surface mount die, the first capacitor die entirely within the footprint of the surface mount die, wherein the first capacitor die is a first silicon-based capacitor die and is a first single-sided capacitor die;
a second capacitor die below the surface mount die, the second capacitor die entirely within the footprint of the surface mount die, and the second capacitor die laterally spaced apart from the first capacitor die, wherein the second capacitor die is a second silicon-based capacitor die and is a second single-sided capacitor die; and
a third capacitor die below the surface mount die, the third capacitor die entirely within the footprint of the surface mount die, and the third capacitor die laterally spaced apart from the second capacitor die, wherein the third capacitor die is a third silicon-based capacitor die and is a third single-sided capacitor die.

18. The package of claim 17 , wherein the bridge die is laterally spaced apart from the first capacitor die.

19. The package of claim 17 , wherein the first die is a processor die.

20. The package of claim 17 , wherein the bridge die is an embedded interconnect bridge (EMIB) die.

Assignees

• Intel Corp

Inventors

• Collins Andrew
• Sharan Sujit
• Xie Jianyong

Classifications

• H10W44/243

  for decoupling, e.g. bypass capacitors · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/614 Primary

  the multiple chips being integrally enclosed · CPC title