Crest factor reduction cancellation pulse having a reduced length
US-12598101-B2 · Apr 7, 2026 · US
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Rajamani Kannan patents
Rajamani Kannan is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Rajamani Kannan |
| Total patents | 21 |
| First publication | Apr 16, 2015 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Analog-to-digital converter system, receiver, base station, mobile device and method for analog-to-digital conversion
US-12494791-B2 · Dec 9, 2025 · US
Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture
US-12490272-B2 · Dec 2, 2025 · US
Apparatus, method, base station, and mobile user equipment for processing undersampled signal
US-2025211247-A1 · Jun 26, 2025 · US
Method and apparatus for digital pre-distortion adaptation
US-2025211265-A1 · Jun 26, 2025 · US
Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture
US-12314216-B2 · May 27, 2025 · US
Hybrid hardware accelerator and programmable array architecture
US-12314217-B2 · May 27, 2025 · US
Method and apparatus for crest factor reduction
US-2024223228-A1 · Jul 4, 2024 · US
Digital pre-distortion (dpd) adaptation flow and accompanying interfaces implemented in a programmable processing array
US-2024220445-A1 · Jul 4, 2024 · US
Apparatus for controlling an equalizer, signal processing system, receiver, base station, mobile device, method for controlling an equalizer
US-2024214248-A1 · Jun 27, 2024 · US
Recent patents
Latest publications not already listed above.
Analog-to-digital converter system, receiver, base station, mobile device and method for analog-to-digital conversion
US-2024187012-A1 · Jun 6, 2024 · US
Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver
US-12003248-B2 · Jun 4, 2024 · US
Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture
US-2024008045-A1 · Jan 4, 2024 · US
Crest factor reduction using peak cancellation without peak regrowth
US-2024004957-A1 · Jan 4, 2024 · US
Crest factor reduction cancellation pulse having a reduced length
US-2024007337-A1 · Jan 4, 2024 · US
Hybrid hardware accelerator and programmable array architecture
US-2023205730-A1 · Jun 29, 2023 · US
Digital pre-distortion (dpd) adaptation using a hybrid hardware accelerator and programmable array architecture
US-2023205727-A1 · Jun 29, 2023 · US
Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver
US-2022200616-A1 · Jun 23, 2022 · US
De-interleaving on an as-needed basis
US-9262350-B2 · Feb 16, 2016 · US
Configurable Transmitter Hardware Block and Methods
US-2016028514-A1 · Jan 28, 2016 · US
De-interleaving on an as-needed basis
US-2015106577-A1 · Apr 16, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 19 |
| Lsi Corp | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04B1/0475 | 5 |
| G06F15/7867 | 4 |
| G06F15/7807 | 4 |
| G06F15/80 | 3 |
| H04L27/2624 | 3 |