De-interleaving on an as-needed basis

Patent metadata

Field	Value
Publication number	US-9262350-B2
Application number	US-201314052911-A
Country	US
Kind code	B2
Filing date	Oct 14, 2013
Priority date	Oct 14, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.

First claim

What is claimed is:

1. An apparatus comprising:
memory configured to store portions of a set of interleaved values, wherein the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values;
a controller configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory; and
a de-interleaving module configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that a processing module downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module, wherein the processing module downstream of the de-interleaving module comprises at least one of:
a removal module configured to begin removing at least one of an acknowledgement message, and a negative acknowledgement message from the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module,
a de-rate matching module configured to begin de-rate matching on the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module; and
a hybrid automatic-repeat request module configured to begin hybrid automatic-repeat request combining on the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.

2. The apparatus of claim 1 , comprising a digital signal processor, wherein the digital signal processor comprises the memory, the controller, and the de-interleaving module.

3. The apparatus of claim 2 , wherein the controller is a direct-memory access controller; and the other memory comprises memory external to the digital signal processor.

4. The apparatus of claim 1 , wherein the apparatus comprises the removal module, the de-rate matching module, and the hybrid automatic-repeat request module.

5. The apparatus of claim 1 , wherein: the interleaved values in the set of interleaved values are arranged into N groups of interleaved values; each portion comprises N subsets of interleaved values, one subset from each of the N groups of interleaved values; and the controller is configured to retrieve, for each portion, the N subsets of interleaved values from the other memory.

6. The apparatus of claim 1 , wherein each interleaved value is a tuple comprising one or more elements.

7. The apparatus of claim 6 , wherein each element is a soft-output value.

8. The apparatus of claim 6 , wherein each tuple comprises information for one modulated symbol modulated using a digital modulation scheme.

9. A method comprising:
(a) retrieving portions of a set of interleaved values from a memory that stores the set of interleaved values, wherein the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values;
(b) de-interleaving the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved; and
(c) performing the processing downstream of the de-interleaving by at least one of: (c1) removal of at least one of, an acknowledgement message, and a negative acknowledgement message from the de-interleaved portion; (c2) de-rate matching on the de-interleaved portion;
and (c3) hybrid automatic-repeat request combining on the de-interleaved portion.

10. The method of claim 9 , wherein step (c) comprises beginning steps (c1)-(c3) before all of the interleaved values in the set of interleaved values are de-interleaved.

11. The method of claim 9 , wherein: the interleaved values in the set of interleaved values are arranged into N groups of interleaved values; each portion comprises N subsets of interleaved values, one subset from each of the N groups of interleaved values; and
step (c) retrieves, for each portion, the N subsets of interleaved values from the other memory.

12. The method of claim 9 , wherein each interleaved value is a tuple comprising one or more elements.

13. The method of claim 12 , wherein each element is a soft-output value.

14. The method of claim 12 , wherein each tuple comprises information for one modulated symbol modulated using a digital modulation scheme.

Assignees

• Intel Corp

Inventors

• Rajamani Kannan
• Sanchez Ramon
• Kinney Kevin R

Classifications

• G06F13/1647 Primary

  with interleaved bank access · CPC title

• H03M13/27

  using interleaving techniques · CPC title

• H04L1/0071 Primary

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H04L1/0068

  by puncturing · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title