Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture

Patent metadata

Field	Value
Publication number	US-12490272-B2
Application number	US-202217853194-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.

First claim

What is claimed is:

1 . A system on a chip (SoC), comprising:
a first buffer configured to store a predetermined number of transmit (TX) data samples identified with a first data transmission from among a plurality of sequential data transmissions; a second buffer configured to store a predetermined number of receive (RX) data samples identified with a data reception obtained via a feedback measurement that is performed with respect to the predetermined number of TX data samples that are transmitted in accordance with the first data transmission; a processing array configured to compute digital pre-distortion (DPD) parameters using (i) the predetermined number of TX data samples, and (ii) the predetermined number of RX data samples, which are accessed from the first and second buffer, respectively, in a time-aligned manner with one another; and a hardware accelerator configured to apply, to data samples identified with a second data transmission from among the plurality of sequential data transmissions, DPD terms in accordance with the computed DPD parameters.

2 . The SoC of claim 1 , wherein the predetermined number of TX data samples and the predetermined number of RX data samples are provided to the processing array in a time-aligned manner based upon a base station frame number (BFN) counter.

3 . The SoC of claim 1 , wherein:
the predetermined number of TX data samples are stored in the first buffer referenced to a first base station frame number (BFN) counter time, the predetermined number of RX data samples are stored in the second buffer referenced to a second BFN counter time, and wherein a difference between the first and the second BFN counter time is based upon a predetermined latency time value such that the predetermined number of TX data samples and the predetermined number of RX data samples are provided to the processing array in the time-aligned manner.

4 . The SoC of claim 1 , further comprising:
a counter having a predetermined counter value, and latch logic configured to increment the counter in response to each one of a number of TX data samples being sequentially transferred along a transmit path to the hardware accelerator, and to begin latching the TX data samples identified with the first data transmission when the number of TX data samples matches the predetermined counter value.

5 . The SoC of claim 4 , wherein the latch logic is configured, upon the number of TX data samples matching the predetermined counter value, to continue to latch the TX data samples until a number of TX data samples have been latched that are equal to the predetermined number of TX data samples, which are then stored in the first buffer.

6 . The SoC of claim 4 , wherein the predetermined counter value corresponds to a time that is aligned with a base station frame number (BFN) counter time.

7 . The SoC of claim 4 , further comprising:
a further hardware accelerator configured to upconvert data samples received via a digital data stream, and to generate, as the TX data samples identified with the first data transmission, upconverted TX data samples.

8 . The SoC of claim 7 , wherein the latch logic is configured to increment the counter in response to each one of a number of the upconverted TX data samples being sequentially transferred from the further hardware accelerator along the transmit path to the hardware accelerator.

9 . The SoC of claim 1 , wherein the predetermined number of TX data samples and the predetermined number of RX data samples are provided to the processing array in a time-aligned manner over multiple clock cycles, each one of the multiple clock cycles being time-referenced to a respective base station frame number (BFN) counter time.

10 . The SoC of claim 1 , wherein the hardware accelerator is configured to apply the DPD terms in accordance with the computed DPD parameters to TX data samples identified with the second data transmission during a downlink (DL) time slot scheduled in accordance with a communication protocol utilized for the plurality of sequential data transmissions.

11 . A system on a chip (SoC), comprising:
a buffer configured to store (i) a predetermined number of transmit (TX) data samples identified with a first data transmission from among a plurality of sequential data transmissions, and (ii) a predetermined number of receive (RX) data samples identified with a data reception obtained via a feedback measurement that is performed with respect to the predetermined number of TX data samples that are transmitted in accordance with the first data transmission; a processing array configured to compute digital pre-distortion (DPD) parameters using (i) the predetermined number of TX data samples, and (ii) the predetermined number of RX data samples, which are accessed from the buffer in a time-aligned manner with one another; and a hardware accelerator configured to apply, to data samples identified with a second data transmission from among the plurality of sequential data transmissions, DPD terms in accordance with the computed DPD parameters.

12 . The SoC of claim 11 , wherein the predetermined number of TX data samples and the predetermined number of RX data samples are provided to the processing array in a time-aligned manner based upon a base station frame number (BFN) counter.

13 . The SoC of claim 11 , wherein the predetermined number of TX data samples are stored in the buffer referenced to a first base station frame number (BFN) counter time, and
wherein the predetermined number of RX data samples are stored in the buffer referenced to a second BFN counter time.

14 . The SoC of claim 13 , wherein a difference between the first and the second BFN counter time is based upon a predetermined latency time value such that the predetermined number of TX data samples and the predetermined number of RX data samples are provided to the processing array in the time-aligned manner.

15 . The SoC of claim 11 , further comprising:
a further hardware accelerator configured to upconvert data samples received via a digital data stream, and to generate, as the TX data samples identified with the first data transmissions, upconverted TX data samples.

16 . The SoC of claim 11 , wherein the predetermined number of TX data samples and the predetermined number of RX data samples are provided to the processing array in a time-aligned manner over multiple clock cycles, each one of the multiple clock cycles being time-referenced to a respective base station frame number (BFN) counter time.

17 . The SoC of claim 11 , wherein the hardware accelerator is configured to apply the DPD terms in accordance with the computed DPD parameters to TX data samples identified with a second data transmission during a downlink (DL) time slot scheduled in accordance with a communication protocol utilized for the plurality of sequential data transmissions.

18 . The SoC of claim 11 , wherein the predetermined number of TX data samples stored in the buffer comprise data samples generated via the processing array as a result of processing operations that are performed on a further predetermined number of TX data samples identified with the first data transmission.

19 . The SoC of claim 11 , wherein the predetermined number of TX data samples stored in the buffer comprise data samples generated via the hardware accelerator by applying further computed DPD parameters associated with a previous data transmission on a further predetermined number of TX data samples identified with the first data tra

Assignees

• Intel Corp

Inventors

• Rajamani Kannan
• Azadet Kameran
• Kinney Kevin
• Smith Thomas
• Zivkovic Zoran

Classifications

• H04J3/0661

  using timestamps · CPC title

• G06N3/063

  using electronic means · CPC title

• H04W72/23 Primary

  in the downlink direction of a wireless link, i.e. towards a terminal · CPC title

• H04L25/03343 Primary

  Arrangements at the transmitter end · CPC title