Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver

Patent metadata

Field	Value
Publication number	US-12003248-B2
Application number	US-202017131819-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.

First claim

What is claimed is:

1. A transceiver comprising:
a transmit path including circuitries configured to process a transmit signal;
a receive path including circuitries configured to process a receive signal;
an observation path including circuitries configured to supply a reference signal for calibration of the transmit path and/or the receive path, wherein the observation path includes:
an analog buffer configured to supply a signal sensed from the transmit path or the receive path; and
an observation analog-to-digital converter (ADC) configured to digitize the signal supplied from the analog buffer, and

a controller configured to generate a first control signal to control sampling events at the observation ADC and send the first control signal to the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants.

2. The transceiver of claim 1 , wherein the controller is configured to generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not, wherein digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid.

3. The transceiver of claim 2 , wherein the observation path further includes a circuitry configured to discard the digital data indicated as invalid and forward the digital data indicated as valid to a non-linear equalizer in the receive path or to a digital pre-distortion circuitry in the transmit path based on the second control signal.

4. The transceiver of claim 1 , wherein the controller is configured to add a random delay value to a fixed sampling period at every predetermined number of sampling instants to generate the first control signal.

5. The transceiver of claim 4 , wherein the controller includes a linear feedback shift register (LFSR) to generate the random delay value.

6. The transceiver of claim 1 , wherein the controller is configured to activate the observation ADC at a fraction of sampling rate of an ADC in a main receive path or a digital-to-analog converter (DAC) in a transmit path.

7. The transceiver of claim 2 , wherein the controller comprises:
a random delay value generation circuit configured to generate a random delay value;
a counter configured to generate an integer count value;
a logic circuit configured determine whether the integer count value is equal to a predetermined value;
a multiplexer configured to output either the random delay value or zero depending on an output of the logic circuit, wherein the random delay value is selected by the multiplexer if the integer count value is equal to the predetermined value and zero is selected by the multiplexer if the integer count value is not equal to the predetermined value; and
an adder configured to add a fixed delay value to an output of the multiplexer to generate the first control signal.

8. The transceiver of claim 7 , wherein the controller further comprises:
a second logic circuit configured to determine whether the integer count value is equal to or greater than a second predetermined value; and
a second multiplexer configured to output either zero or one as the second control signal based on an output of the second logic circuit.

9. The transceiver of claim 7 , wherein the counter is configured to generate the integer count value within a range from zero to P−1, wherein the parameter P is adjustable.

10. The transceiver of claim 7 , wherein the random delay value generation circuit is configured to generate the random delay value within a range from zero to M−1, wherein the parameter M is adjustable.

11. A method for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver, comprising:
supplying a signal sensed from a transmit path or a receive path to an observation ADC in the observation path;
generating a first control signal to control sampling events at the observation ADC;
sending the first control signal to the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants; and
digitizing, by the observation ADC, the signal supplied based on the first control signal.

12. The method of claim 11 , further comprising:
generating a second control signal indicating whether digital data generated by the observation ADC is valid or not, wherein digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid;
discarding the digital data indicated as invalid; and
forwarding the digital data indicated as valid to a non-linear equalizer in the receive path or to a digital pre-distortion circuitry in the transmit path.

13. The method of claim 11 , wherein the first control signal is generated by introducing a random delay value to a fixed sampling period at every predetermined number of sampling instants.

14. The method of claim 13 , wherein the random delay value is generated by a linear feedback shift register (LFSR).

15. The method of claim 11 , wherein the observation ADC is activated at a fraction of sampling rate of an ADC in a main receive path or a digital-to-analog converter (DAC) in a transmit path.

16. The method of claim 12 , wherein the first control signal is generated by:
generating a random delay value;
generating an integer count value;
determining, by a first logic circuit, whether the integer count value is equal to a predetermined value;
outputting, by a multiplexer, either the random delay value or zero depending on an output of the first logic circuit, wherein the random delay value is output if the integer count value is equal to the predetermined value and zero is output if the integer count value is not equal to the predetermined value; and
adding a fixed delay value to an output of the multiplexer to generate the first control signal.

17. The method of claim 16 , wherein the second control signal is generated by:
determining, by a second logic circuit, whether the integer count value is equal to or greater than a second predetermined value; and
outputting either zero or one as the second control signal based on an output of the second logic circuit.

18. A system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver, comprising:
a controller configured to generate a control signal to control sampling events at an ADC and send the control signal to the ADC to activate the ADC at combined uniform and non-uniform sampling instants.

19. The system of claim 18 , wherein the controller is configured to indicate digital data generated by the ADC at non-uniform sampling instants as invalid and digital data generated by the ADC at uniform sampling instants as valid.

20. The system of claim 18 , wherein the controller comprises:
a random delay value generation circuit configured to generate a random delay value;
a counter configured to output an integer count value;
a logic circuit configured determine whether the integer count value is equal to a predetermined value;
a multiplexer configured to output either the random delay value or zero depending on an output of the logic circuit, wherein the random delay value is selected if the output of the counter is equal to the predetermined value and zero is selected if the output of the counter is not equal to the predetermined value; and
an adde

Assignees

• Intel Corp

Inventors

• Camponeschi Matteo
• Molina Albert
• Rajamani Kannan
• Cascio Giacomo
• Lindholm Christian

Classifications

• H03M1/1009 Primary

  Calibration · CPC title

• H04B1/40

  Circuits · CPC title

• H04L5/0048

  Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091) · CPC title

• H03M1/1265 Primary

  Non-uniform sampling · CPC title

• H04B1/0003

  Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain (digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00) · CPC title