Analog-to-digital converter system, receiver, base station, mobile device and method for analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-2024187012-A1
Application number	US-202118553212-A
Country	US
Kind code	A1
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Jun 6, 2024
Grant date	—

Abstract

An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

First claim

1 . An analog-to-digital converter, ADC, system, comprising:
a first signal path comprising:
a first ADC configured to generate first digital data based on an input signal, the first ADC being a time-interleaved ADC comprising a plurality of sub-ADCs; and
circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active;
a correction circuit configured to output digital correction data based on the activity data; a second signal path coupled in parallel to the first signal path, the second signal path comprising:
a second ADC configured to generate second digital data based on the input signal; and
a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data; and
an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data, wherein the equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

2 . The ADC system according to claim 1 , wherein
the first ADC is configured to sample the input signal at a first sampling frequency and the second ADC is configured to sample the input signal at a second sampling frequency being lower than the first sampling frequency.

3 . The ADC system according to claim 1 , wherein
the combiner circuit is configured to generate modified second digital data by subtracting the correction data from the second digital data or adding the correction data to the second digital data.

4 . The ADC system according to claim 1 , wherein
the correction circuit comprises a look-up table, and the correction circuit is configured to select an entry of the look-up table based on the sub-ADC indicated as currently active in the activity data and output the selected entry of the look-up table as the correction data.

5 . The ADC system according to claim 4 , wherein
the look-up table is a one-dimensional look-up table comprising N entries, N being the number of sub-ADCs of the first ADC.

6 . The ADC system according to claim 1 , wherein
the activity data further indicate one or more previously active sub-ADCs of the plurality of sub-ADCs.

7 . The ADC system according to claim 6 , wherein
the correction circuit comprises a look-up table, and the correction circuit is configured to: select an entry of the look-up table based on the sub-ADC indicated as currently active in the activity data and the one or more previously active sub-ADCs indicated in the activity data; and output the selected entry of the look-up table as the correction data.

8 . The ADC system according to claim 7 , wherein
the look-up table is of dimension N k with N being the number of sub-ADCs of the first ADC and k−1 being the number of the one or more previously active sub-ADCs indicated in the activity data.

9 . The ADC system according to claim 6 , wherein
the correction circuit comprises k look-up tables, and the correction circuit is configured to: select a respective entry of each of the k look-up tables based on respective one of the sub-ADC indicated as currently active in the activity data and the one or more previously active sub-ADCs indicated in the activity data; and output the selected entries of the k look-up tables as the correction data.

10 . The ADC system according to claim 9 , wherein
the k look-up tables are one-dimensional look-up tables each comprising N entries, N being the number of sub-ADCs of the first ADC and k−1 being the number of the one or more previously active sub-ADCs indicated in the activity data.

11 . The ADC system according to claim 1 , wherein
the circuitry is configured to determine the activity data based on the first digital data.

12 . The ADC system according to claim 1 , wherein
the first signal path further comprises a first buffer circuit configured to buffer the input signal, and an input of the first ADC is coupled to an output of the first buffer circuit.

13 . The ADC system according to claim 1 , wherein
the second signal path further comprises an attenuator circuit configured to attenuate the input signal and a second buffer circuit configured to buffer the input signal, an input of the second ADC is coupled to an output of the second buffer circuit, and an input of the second buffer circuit is coupled to an output of the attenuator circuit.

14 . A receiver, comprising:
an ADC system according to claim 1 ; and analog circuitry configured to receive a receive signal and to supply the input signal to the ADC system based on the receive signal.

15 . The receiver according to claim 14 , wherein
the input signal is a radio frequency signal.

16 . A base station, comprising:
a receiver according to claim 14 ; and a transmitter configured to generate a radio frequency transmit signal.

17 . The base station according to claim 16 , further comprising:
at least one antenna element coupled to at least one of the receiver and the transmitter.

18 . A mobile device, comprising:
a receiver according to claim 14 ; and a transmitter configured to generate a radio frequency transmit signal.

19 . (canceled)

20 . A method for analog-to-digital conversion, comprising:
generating, by a first ADC of a first signal path, first digital data based on an input signal, the first ADC being a time-interleaved ADC comprising a plurality of sub-ADCs; outputting, by circuitry of the first signal path, activity data indicating at least which of the plurality of sub-ADCs is currently active; outputting, by a correction circuit, digital correction data based on the activity data; generating, by a second ADC of a second signal path coupled in parallel to the first signal path, second digital data based on the input signal; generating, by a combiner circuit of the second signal path, modified second digital data by combining the second digital data and the correction data; generating an equalized output signal, by an equalizer and based on the first digital data; and adjusting, by the equalizer and based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal.

21 . The method according to claim 20 , wherein generating the modified second digital data comprises:
subtracting the digital correction data from the second digital data or adding the digital correction data to the second digital data.

Assignees

• Intel Corp

Inventors

• Camponeschi Matteo
• Molina Albert
• Rajamani Kannan
• Clara Martin

Classifications

• H03M1/0609 Primary

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error · CPC title

• H03M1/1042 Primary

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title

• H03M1/188

  Multi-path, i.e. having a separate analogue/digital converter for each possible range · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/0626

  by filtering · CPC title