Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture

Patent metadata

Field	Value
Publication number	US-12314216-B2
Application number	US-202117560685-A
Country	US
Kind code	B2
Filing date	Dec 23, 2021
Priority date	Dec 23, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

First claim

What is claimed is:

1. A system on a chip (SoC), comprising:
an array of processing elements, each one of the processing elements being configured to perform processing operations on an array of data samples corresponding to an input data signal;
a hardware accelerator; and
a data interface coupled to the array of processing elements and to the hardware accelerator, the data interface being configured to transfer the array of data samples from the array of processing elements to the hardware accelerator,
wherein the hardware accelerator is configured to compute digital pre-distortion (DPD) parameters in accordance with a predetermined preprocessing function using the array of data samples transferred via the data interface; and
a power amplifier (PA) configured to transmit an output data signal based upon a set of preprocessed data samples that are generated using the DPD parameters.

2. The SoC of claim 1 , wherein:
one of the array of processing elements is configured to compute additional DPD parameters, and
the data interface is configured to synchronize the additional DPD parameters computed via the one of the array of processing elements with the DPD parameters computed via the hardware accelerator.

3. The SoC of claim 2 , wherein the hardware accelerator comprises summation circuitry configured to add the DPD parameters and the additional DPD parameters to provide a set of combined DPD parameters.

4. The SoC of claim 3 , wherein the set of preprocessed data samples are generated by applying the set of combined DPD parameters to the array of data samples corresponding to the input data signal.

5. The SoC of claim 2 , wherein:
the data interface is configured to transfer a set of output data samples corresponding to the output data signal to one of the array of processing elements, and
the one of the array of processing elements is configured to adapt the DPD parameters by computing modified DPD parameters using the set of output data samples.

6. The SoC of claim 5 , wherein:
the hardware accelerator comprises a set of lookup tables (LUTs), each one of the set of LUTs containing two different sets of data entries,
a first one of the two different sets of data entries corresponds to the DPD parameters, and
a second one of the two different sets of data entries corresponds to the modified DPD parameters.

7. The SoC of claim 6 , wherein the hardware accelerator is configured to compute the DPD parameters or the modified DPD parameters by correlating the array of data samples transferred via the data interface to one of the first or the second one of the two different sets of data entries, respectively, in response to a control signal received via the data interface.

8. The SoC of claim 1 , wherein the hardware accelerator comprises a set of lookup tables (LUTs), each one of the set of LUTs containing data entries corresponding to the DPD parameters, and
wherein the hardware accelerator is configured to compute the DPD parameters in accordance with the predetermined preprocessing function by correlating the array of data samples transferred via the data interface to the data entries in the set of LUTs.

9. The SoC of claim 1 , wherein:
the data interface is configured to transfer a set of DPD parameter data samples corresponding to the DPD parameters computed via the hardware accelerator to one of the array of processing elements, and
the one of the array of processing elements is configured to generate the set of preprocessed data samples by computing a first set of modified DPD parameters using the DPD parameters, and applying the first set of modified DPD parameters to the array of data samples corresponding to the input data signal.

10. The SoC of claim 9 , wherein:
the data interface is configured to transfer a set of output data samples corresponding to the output data signal to one of the array of processing elements, and
the one of the array of processing elements is configured to adapt the first set of modified DPD parameters by computing a second set of modified DPD parameters using the set of output data samples.

11. The SoC of claim 10 , wherein:
the hardware accelerator comprises a set of lookup tables (LUTs), each one of the set of LUTs containing two different sets of data entries,
a first one of the two different sets of data entries corresponds to the first set of modified DPD parameters, and
a second one of the two different sets of data entries corresponds to the second set of modified DPD parameters.

12. The SoC of claim 11 , wherein the hardware accelerator is configured to compute the first set of modified DPD parameters or the second set of modified DPD parameters by correlating the array of data samples transferred via the data interface to one of the first or the second one of the two different sets of data entries, respectively, in response to a control signal received via the data interface.

13. A wireless device, comprising:
an array of processing elements, each one of the processing elements being configured to perform processing operations on an array of data samples corresponding to an input data signal;
a hardware accelerator; and
a data interface coupled to the array of processing elements and to the hardware accelerator, the data interface being configured to transfer the array of data samples from the array of processing elements to the hardware accelerator,
wherein the hardware accelerator is configured to compute digital pre-distortion (DPD) parameters in accordance with a predetermined preprocessing function using the array of data samples transferred via the data interface; and
a power amplifier (PA) configured to transmit an output data signal based upon a set of preprocessed data samples that are generated using the DPD parameters.

14. The wireless device of claim 13 , wherein:
one of the array of processing elements is configured to compute additional DPD parameters, and
the data interface is configured to synchronize the additional DPD parameters computed via the one of the array of processing elements with the DPD parameters computed via the hardware accelerator.

15. The wireless device of claim 14 , wherein the hardware accelerator comprises summation circuitry configured to add the DPD parameters and the additional DPD parameters to provide a set of combined DPD parameters.

16. The wireless device of claim 15 , wherein the set of preprocessed data samples are generated by applying the set of combined DPD parameters to the array of data samples corresponding to the input data signal.

17. The wireless device of claim 14 , wherein:
the data interface is configured to transfer a set of output data samples corresponding to the output data signal to one of the array of processing elements, and
the one of the array of processing elements is configured to adapt the DPD parameters by computing modified DPD parameters using the set of output data samples.

18. The wireless device of claim 17 , wherein:
the hardware accelerator comprises a set of lookup tables (LUTs), each one of the set of LUTs containing two different sets of data entries,
a first one of the two different sets of data entries corresponds to the DPD parameters, and
a second one of the two different sets of data entries corresponds to the modified DPD parameters.

19. The wireless device of claim 18 , wherein the hardware accelerator is configured to compute the DPD parameters or the modified DPD parameters by correlating the array of data samples transferred via the data interface to one of

Assignees

• Intel Corp

Inventors

• Zivkovic Zoran
• Azadet Kameran
• Rajamani Kannan
• Smith Thomas

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F15/7889

  Reconfigurable logic implemented as a co-processor (instruction execution using a coprocessor G06F9/3877) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/7807 Primary

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title