Bottom package with metal post interconnections
US-10971476-B2 · Apr 6, 2021 · US
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Radojcic Ratibor patents
Radojcic Ratibor is listed as an inventor on 17 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Radojcic Ratibor |
| Total patents | 17 |
| First publication | Jul 30, 2015 |
| Latest publication | Apr 6, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Substrate block for PoP package
US-9881859-B2 · Jan 30, 2018 · US
Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems
US-9869713-B2 · Jan 16, 2018 · US
Integrated circuit (IC) package comprising electrostatic discharge (ESD) protection
US-9853446-B2 · Dec 26, 2017 · US
Integrated device comprising a capacitor that includes multiple pins and at least one pin that traverses a plate of the capacitor
US-9704796-B1 · Jul 11, 2017 · US
Integrated device comprising flexible connector between integrated circuit (IC) packages
US-9633977-B1 · Apr 25, 2017 · US
Integrated circuit (ic) package comprising electrostatic discharge (esd) protection
US-2017063079-A1 · Mar 2, 2017 · US
Anchoring conductive material in semiconductor devices
US-2017005160-A1 · Jan 5, 2017 · US
THROUGH-SILICON VIA (TSV) CRACK SENSORS FOR DETECTING TSV CRACKS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs), AND RELATED METHODS AND SYSTEMS
US-2016258996-A1 · Sep 8, 2016 · US
Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US-9418877-B2 · Aug 16, 2016 · US
Recent patents
Latest publications not already listed above.
Semiconductor package with incorporated inductance element
US-2016133614-A1 · May 12, 2016 · US
Method and apparatus for characterizing thermal marginality in an integrated circuit
US-9285418-B2 · Mar 15, 2016 · US
SUBSTRATE BLOCK FOR PoP PACKAGE
US-2015325509-A1 · Nov 12, 2015 · US
Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US-2015318262-A1 · Nov 5, 2015 · US
Enhanced package thermal management using external and internal capacitive thermal material
US-9136202-B2 · Sep 15, 2015 · US
Bottom package with metal post interconnections
US-2015235991-A1 · Aug 20, 2015 · US
Integrated device comprising a substrate with aligning trench and/or cooling cavity
US-2015214127-A1 · Jul 30, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 17 |
| Chiriac Victor A | 1 |
| Lisk Durodami J | 1 |
| Radojcic Ratibor | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 12 |
| H10W70/60 | 10 |
| H10W90/00 | 10 |
| H10W90/722 | 8 |
| H10W72/252 | 7 |