Substrate block for PoP package

Patent metadata

Field	Value
Publication number	US-9881859-B2
Application number	US-201414273882-A
Country	US
Kind code	B2
Filing date	May 9, 2014
Priority date	May 9, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

First claim

We claim:

1. A device comprising: a die comprising a first die surface and a second die surface, wherein the first die surface is on an opposite side to the second die surface; a carrier comprising a plurality of vertical interconnections; a first bar coupled to the vertical interconnections, wherein the first bar has a first bar width and comprises a substrate and a plurality of filled vias through the substrate, and wherein the first bar width extends to and aligns with a lateral edge of the carrier, and wherein the first bar is adjacent to the first die surface; a second bar separate from the first bar, the second bar having a second bar width and coupled to the vertical interconnections and comprising an additional substrate, and wherein the second bar width extends to and aligns with the lateral edge of the carrier, and wherein the second bar is adjacent to the second die surface; and an encapsulant, wherein the die, the first bar and the second bar are embedded in the encapsulant, wherein the first bar has a via pattern and the second bar is devoid of a via pattern.

2. The device of claim 1 , wherein the substrate comprises silicon, organic material, or glass.

3. The device of claim 1 , further comprising contact pads on first and second surfaces of the substrate.

4. The device of claim 1 , wherein the first bar is exposed on at least one side.

5. The device of claim 4 , wherein a lateral side of the first bar is exposed.

6. The device of claim 4 , wherein a side of the first bar perpendicular to the plurality of filled vias is exposed.

7. The device of claim 1 , wherein the filled vias comprise copper.

8. A package substrate, comprising:
a carrier comprising a plurality of vertical interconnections;
a first bar coupled to the vertical interconnections, the first bar having a first bar width and comprising a plurality of filled vias surrounded by a substrate material, wherein the first bar width extends to and aligns with a lateral edge of the carrier, and wherein the plurality of filled vias extend from one bar surface to a second bar surface;
a die comprising a first die surface and a second die surface, wherein the first die surface is on an opposite side to the second die surface, and wherein the die is coupled to the vertical interconnections and the first bar is adjacent to the first die surface;
a second bar separate from the first bar and the die, the second bar having a second bar width and coupled to the vertical interconnections, and a plurality of additional filled vias and wherein the second bar width extends to and aligns with the lateral edge of the carrier, and wherein the second bar is adjacent to the second die surface; and wherein the first bar extends laterally to align with a lateral edge of the carrier so as to be exposed on at least one side; and
an encapsulant, wherein the die, the first bar and the second bar are embedded in the encapsulant,
wherein the plurality of the filled vias of the first bar are arranged in a first via pattern and the plurality of additional filled vias of the second bar are arranged in a second via pattern different than the first via pattern.

9. The package substrate of claim 8 , wherein the carrier comprises silicon.

10. The package substrate of claim 8 , wherein the first bar width is about 800 μm.

11. The package substrate of claim 8 , wherein the substrate material comprises silicon, organic material, or glass.

12. The package substrate of claim 8 , further comprising a molding compound that covers the die and is disposed in between the first bar and the die.

13. The package substrate of claim 8 , included in a package on package (PoP) structure.

14. The PoP structure of claim 13 , further comprising a second package substrate coupled to the package substrate through an interconnection.

15. The PoP structure of claim 13 , wherein the plurality of filled vias and vertical interconnections are configured to route signals through the package substrate.

16. The PoP structure of claim 13 , wherein the PoP structure is incorporated into at least one of a cellphone, a laptop, a tablet, a music player, a communication device, a computer, and a video player.

17. A device, comprising:
a carrier comprising a plurality of vertical interconnections;
a first bar coupled to the vertical interconnections, the first bar having a first bar length and a first bar width and comprising means for providing electrical connections between one bar surface and a second opposing bar surface;
a die comprising a first die surface and a second die surface, wherein the first die surface is on an opposite side to the second die surface, and wherein the die is coupled to the vertical interconnections and the first bar is adjacent to the first die surface;
a second bar separate from the first bar and the die, the second bar coupled to the vertical interconnections, and wherein the second bar is adjacent to the second die surface and wherein the first bar width extends laterally to align with a lateral edge of the carrier so as to be exposed on at least one side; and
an encapsulant, wherein the die, the first bar and the second bar are embedded in the encapsulant,
wherein the die comprises a top surface and a bottom surface and opposed edge surfaces extending between the top surface and the bottom surface and between the first die surface and the second die surface, and the first bar length extends to align with at least one of the opposed edge surfaces of the die.

18. The device of claim 17 , wherein the means comprises a plurality of filled vias coupled to the vertical interconnections.

19. The device of claim 17 , wherein the first bar width is about 800 μm.

20. The device of claim 17 , further comprising a molding compound that covers the die and is disposed in between the first bar and the die.

21. The device of claim 17 , wherein the device is included in a package on package (PoP) structure.

22. The device of claim 1 , wherein the second bar comprises an additional lateral edge that aligns with an additional lateral edge of the carrier.

23. The device of claim 1 , wherein the second bar comprises an additional lateral edge that aligns with the lateral edge of the carrier.

24. The device of claim 1 , wherein the second bar is exposed on at least one side.

25. The device of claim 1 , wherein the second bar is exposed on at least one side.

Assignees

• Qualcomm Inc

Inventors

• We Hong Bok
• Kim Dong Wook
• Lee Jae Sik
• Gu Shiqun
• Radojcic Ratibor

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/072

  of bump connectors · CPC title