Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers

Patent metadata

Field	Value
Publication number	US-9418877-B2
Application number	US-201414324136-A
Country	US
Kind code	B2
Filing date	Jul 4, 2014
Priority date	May 5, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

First claim

What is claimed is:

1. An integrated device comprising:
a base portion for the integrated device, the base portion comprising:
a first inorganic dielectric layer;
a first set of interconnects in the first inorganic dielectric layer, wherein the first set of interconnects comprises a first interconnect comprising:
a first seed layer; and
a first metal layer coupled to the first seed layer;

a second dielectric layer different from the first inorganic dielectric layer; and
a second set of interconnects in the second dielectric layer, the second set of interconnects comprising a second interconnect, wherein the second interconnect comprises:
a second seed layer; and
a second metal layer coupled to the second seed layer,
wherein the second interconnect is coupled to the first interconnect such that the second seed layer is directly coupled to the first seed layer;

a first die coupled to a first surface of the base portion; and
a second die coupled to the first surface of the base portion, the second die is configured to electrically couple to the first die through the first set of interconnects.

2. The integrated device of claim 1 , wherein the second dielectric layer is an organic dielectric layer.

3. The integrated device of claim 1 , wherein the first set of interconnects comprises a first spacing that is less than a second spacing of the second set of interconnects.

4. The integrated device of claim 1 , wherein the first set of interconnects comprises a first pitch that is about 4 microns (μm) or less.

5. The integrated device of claim 1 , wherein the first seed layer is coupled to a horizontal portion of the first metal layer and side portions of the first metal layer.

6. The integrated device of claim 1 , wherein the second seed layer is located only on a horizontal planar surface of the first interconnects.

7. The integrated device of claim 1 , wherein the second seed layer is located only on a bottom planar surface of the first set of interconnects.

8. The integrated device of claim 1 , further comprising an encapsulation material that encapsulates the first die and the second die.

9. The integrated device of claim 8 , further comprising a third set of interconnects traversing the encapsulation material, the third set of interconnects configured to operate as a set of package-to-package interconnects in package-on-package (PoP) device.

10. The integrated device of claim 9 , wherein the third set of interconnects comprises one or more of a solder ball, or a through encapsulation via (TEV), or combinations thereof.

11. The integrated device of claim 1 , wherein the first die comprises a first set of interconnect pillars, the first die being configured to electrically couple to the second set of interconnects through the first set of interconnect pillars.

12. The integrated device of claim 1 , wherein the first set of interconnects in the first inorganic dielectric layer comprises a set of vias that couple to the second set of interconnects in the second dielectric layer.

13. The integrated device of claim 1 , wherein the base portion is an interposer.

14. The integrated device of claim 1 , further comprising a third set of interconnects that couple the first die to the base portion.

15. The integrated device of claim 14 , wherein the third set of interconnects includes one or more of an under bump, a copper-copper bonding interconnect with oxide-to-oxide, or a copper-copper/Oxide-Oxide hybrid bonding, or combinations thereof.

16. The integrated device of claim 1 , wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

17. The integrated device of claim 1 , wherein the first set of interconnects comprises a third interconnect that includes a third metal layer and a third seed layer coupled only to a side portion of the third metal layer, and wherein the second set of interconnects comprises a fourth interconnect that includes a fourth seed layer and a fourth metal layer coupled to the fourth seed layer, and wherein the fourth interconnect is coupled to the third interconnect such that the fourth layer is directly coupled to the third metal layer.

18. A method for fabricating an integrated device, comprising:
forming a base portion for the integrated device, wherein forming the base portion comprises:
forming a first inorganic dielectric layer;
forming a first set of interconnects in the first inorganic dielectric layer, wherein forming the first set of interconnects comprises forming a first interconnect that includes a first seed layer and a first metal layer;
forming a second dielectric layer different from the first inorganic dielectric layer; and
forming a second set of interconnects in the second dielectric layer, wherein forming the second set of interconnects comprises forming a second interconnect that includes a second seed layer and a second metal layer, such that the second seed layer is directly coupled to the first seed layer of the first interconnect;

coupling a first die to a first surface of the base portion; and
coupling a second die to the first surface of the base portion such that the second die is configured to electrically couple to the first die through the first set of interconnects.

19. The method of claim 18 , wherein the second dielectric layer is an organic dielectric layer.

20. The method of claim 18 , wherein the first set of interconnects comprises a first spacing that is less than a second spacing of the second set of interconnects.

21. The method of claim 18 , wherein the first set of interconnects comprises a first pitch that is about 4 microns (μm) or less.

22. The method of claim 18 , wherein the first seed layer is coupled to a horizontal portion of the first metal layer and side portions of the first metal layer.

23. The method of claim 18 , wherein the second seed layer is located only on a horizontal planar surface of the first set of interconnects.

24. The method of claim 18 , wherein the second seed layer is located only on a bottom planar surface of the first set of interconnects.

25. The method of claim 18 , further comprising forming an encapsulation material that encapsulates the first die and the second die.

26. The method of claim 25 , further comprising forming a third set of interconnects that traverses the encapsulation material, the third set of interconnects configured to operate as a set of package-to-package interconnects in package-on-package (PoP) device.

27. The method of claim 26 , wherein the third set of interconnects comprises one or more of a solder ball, or a through encapsulation via (TEV), or combinations thereof.

28. The method of claim 18 , wherein the first die comprises a first set of interconnect pillars, the first die being configured to electrically couple to the second set of interconnects through the first set of interconnect pillars.

29. The method of claim 18 , wherein the first set of interconnects in the first inorganic dielectric layer comprises a set of vias that couple to the second set of interconnects in the second dielectric layer.

30. The method of claim

Assignees

• Qualcomm Inc

Inventors

• Gu Shiqun
• Radojcic Ratibor
• Kim Dong Wook
• Lee Jae Sik

Classifications

• H05K3/4688

  Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602) · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title