Anchoring conductive material in semiconductor devices

Patent metadata

Field	Value
Publication number	US-2017005160-A1
Application number	US-201514973479-A
Country	US
Kind code	A1
Filing date	Dec 17, 2015
Priority date	Jul 1, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.

First claim

1 . A semiconductor device, comprising:
a bottom metal with an anchoring cap formed thereon; a metal-insulator-metal (MIM) capacitor formed above the bottom metal; a first top metal electrically coupled to an upper plate of the MIM capacitor through a first capacitor interconnect; and a second top metal electrically coupled to a lower plate of the MIM capacitor through a second capacitor interconnect, wherein at least a portion of the bottom metal overlaps at least a portion of the lower plate of the MIM capacitor.

2 . The semiconductor device of claim 1 , further comprising:
a separation layer formed between the bottom metal and the lower plate of the MIM capacitor so as to electrically separate the bottom metal and the MIM capacitor.

3 . The semiconductor device of claim 2 , wherein a thickness of the separation layer is less than a thickness of the bottom metal.

4 . The semiconductor device of claim 2 , further comprising:
a signal routing path formed below the MIM capacitor, wherein the bottom metal forms at least a part of the signal routing path.

5 . The semiconductor device of claim 1 , wherein the bottom metal is electrically coupled to the lower plate of the MIM capacitor.

6 . The semiconductor device of claim 1 , wherein the bottom metal is formed of copper (Cu).

7 . The semiconductor device of claim 1 , wherein the anchoring cap is formed on an upper surface of the bottom metal facing the lower plate of the MIM capacitor.

8 . The semiconductor device of claim 1 , wherein the anchoring cap is formed of any one or more of Co, Mn, CoWP, CoSnP, and Pd.

9 . The semiconductor device of claim 1 ,
wherein the MIM capacitor includes the lower plate formed above the bottom metal, the upper plate formed above the lower plate, and a dielectric layer sandwiched in between the lower plate and the upper plate, and wherein the upper plate, the dielectric layer, and the lower plate of the MIM capacitor are all substantially flat.

10 . The semiconductor device of claim 9 , wherein the dielectric layer of the MIM capacitor is a high-K dielectric layer.

11 . The semiconductor device of claim 1 , wherein the first top metal and the second top metal are formed above the upper plate of the MIM capacitor.

12 . The semiconductor device of claim 1 , wherein the semiconductor device is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

13 . A method of manufacturing a semiconductor device, the method comprising:
forming a bottom metal with an anchoring cap thereon; forming a metal-insulator-metal (MIM) capacitor above the bottom metal; forming a first top metal electrically coupled to an upper plate of the MIM capacitor through a first capacitor interconnect; and forming a second top metal electrically coupled to a lower plate of the MIM capacitor through a second capacitor interconnect, wherein the semiconductor device is formed such that at least a portion of the bottom metal overlaps at least a portion of the lower plate of the MIM capacitor.

14 . The method of claim 13 , further comprising:
forming a separation layer between the bottom metal and the lower plate of the MIM capacitor so as to electrically separate the bottom metal and the MIM capacitor.

15 . The method of claim 14 , wherein the separation layer is formed such that a thickness of the separation layer is less than a thickness of the bottom metal.

16 . The method of claim 14 , further comprising:
forming a signal routing path below the MIM capacitor, wherein the bottom metal is formed such that the bottom metal is at least a part of the signal routing path.

17 . The method of claim 13 , wherein the bottom metal is formed to be electrically coupled to the lower plate of the MIM capacitor.

18 . The method of claim 13 , wherein the anchoring cap is formed on an upper surface of the bottom metal facing the lower plate of the MIM capacitor.

19 . The method of claim 13 ,
wherein forming the MIM capacitor comprises:
forming the lower plate above the bottom metal;
forming the upper plate above the lower plate; and
forming a dielectric layer so as to be sandwiched in between the lower plate and the upper plate, and
wherein the upper plate, the dielectric layer, and the lower plate of the MIM capacitor are all formed to be substantially flat.

20 . The method of claim 19 , wherein the dielectric layer of the MIM capacitor is formed with a high-K dielectric layer.

21 . The method of claim 13 , wherein the first top metal and the second top metal are formed above the upper plate of the MIM capacitor.

22 . A semiconductor device, comprising:
a metal-insulator-metal (MIM) capacitor; and a top metal formed on the MIM capacitor, wherein the MIM capacitor comprises:
a bottom metal with an anchoring cap formed thereon,
a dielectric layer formed on the bottom metal, and
a capacitor interconnect formed on the dielectric layer, and
wherein the top metal is formed on and is electrically coupled to the capacitor interconnect.

23 . The semiconductor device of claim 22 , wherein the anchoring cap is formed on an upper surface of the bottom metal facing the dielectric layer such that the dielectric layer is formed on at least a portion of the anchoring cap.

24 . The semiconductor device of claim 23 , wherein the anchoring cap is also formed on a side surface of the bottom metal.

25 . The semiconductor device of claim 22 , wherein the dielectric layer extends from a side surface of the bottom metal.

26 . A method of manufacturing a semiconductor device, the method comprising:
forming a metal-insulator-metal (MIM) capacitor; and forming a top metal on the MIM capacitor, wherein forming the MIM capacitor comprises:
forming a bottom metal and an anchoring cap on the bottom metal;
forming a dielectric layer on the bottom metal; and
forming a capacitor interconnect on the dielectric layer, and
wherein the top metal is formed on and electrically coupled to the capacitor interconnect.

27 . The method of claim 26 , wherein the anchoring cap is formed on an upper surface of the bottom metal facing the dielectric layer such that the dielectric layer is formed on at least a portion of the anchoring cap.

28 . The method of claim 27 , wherein the anchoring cap is also formed on a side surface of the bottom metal.

29 . The method of claim 26 , wherein the dielectric layer is formed to extend from a side surface of the bottom metal.

Assignees

• Qualcomm Inc

Inventors

• Gu Shiqun
• Li Yue
• Radojcic Ratibor

Classifications

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H01L23/5223

  Electricity · mapped topic