Method and apparatus for characterizing thermal marginality in an integrated circuit

Patent metadata

Field	Value
Publication number	US-9285418-B2
Application number	US-201313793880-A
Country	US
Kind code	B2
Filing date	Mar 11, 2013
Priority date	Apr 30, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.

First claim

What is claimed is:

1. A method for testing integrated circuit (IC) performance, comprising:
generating, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the generating the one or more thermal hot spots in one or more core blocks comprises exciting at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block; and
initiating one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one of the one or more thermal hot spots is present.

2. The method of claim 1 , wherein generating the one or more thermal hot spots comprises:
determining when the at least one core block reaches a specified temperature based on the thermal profile.

3. The method of claim 1 , further comprising:
upon completing a test of one or more components of the IC when a first thermal hot spot is present, performing another test of the one or more components of the IC when a second thermal hot spot is present in a location different from or in addition to a location of the first thermal hotspot.

4. The method of claim 2 , wherein exciting the at least one core block of the IC comprises turning on at least one circuit in the core block via a design for test structure on the IC.

5. The method of claim 1 , wherein the one or more hot spots mimic a temperature condition present during a functional test of the IC.

6. The method of claim 2 , wherein determining when the at least one core block reaches a specified temperature comprises:
periodically reading one or more registers associated with one or more temperature sensors on the IC, wherein the registers are read via a design for test structure on the IC.

7. The method of claim 1 , wherein the IC is a two-dimensional or a three-dimensional IC.

8. The method of claim 1 , wherein the one more tests further comprise one or more of a memory built-in self-test or a logic built-in self-test, or an at speed through-silicon-via (TSV) test.

9. The method of claim 1 , wherein generating the one or more thermal hot spots further comprises:
connecting the design-for-test structure, via a first connection chain, to a plurality of temperature sensors on the IC;
connecting the design-for-test structure, via a second connection chain, to a control register in each of the plurality of core blocks on the IC;
transmitting a first instruction, via the design-for-test structure, to at least one core block on the IC to trigger operation of the core block; and
transmitting a second instruction, via the design-for-test structure, to periodically check the temperature of one or more of the plurality of temperature sensors until a desired temperature is reached.

10. The method of claim 9 , wherein triggering operation of the core block comprises feeding one or more structural vectors into the core block to trigger its operation.

11. The method of claim 10 , wherein the structural vectors are fed into the core block via external automated test equipment.

12. The method of claim 11 , wherein the structural vectors are generated on the IC.

13. An apparatus for testing integrated circuit (IC) performance, comprising:
means for generating, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the means for generating the one or more thermal hot spots in one or more core blocks is configured to excite at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block; and
means for initiating one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one of the one or more thermal hot spots is present.

14. The apparatus of claim 13 , wherein the means for wherein generating the one or more thermal hot spots comprises:
means for determining when the at least one core block reaches a specified temperature based on the thermal profile.

15. The apparatus of claim 13 , further comprising:
upon completing a test of one or more components of the IC when a first thermal hot spot is present, means for performing another test of the one or more components of the IC when a second thermal hot spot is present in a location different from or in addition to a location of the first thermal hotspot.

16. The apparatus of claim 14 , wherein the means for exciting the at least one core block of the IC comprises means for turning on at least one circuit in the core block via a design for test structure on the IC.

17. The apparatus of claim 13 , wherein the one or more hot spots mimic a temperature condition present during a functional test of the IC.

18. The apparatus of claim 14 , wherein the means for determining when the at least one core block reaches a specified temperature comprises:
means for periodically reading one or more registers associated with one or more temperature sensors on the IC,
wherein the registers are read via a design for test structure on the IC.

19. The apparatus of claim 13 , wherein the IC is a two-dimensional or a three-dimensional IC.

20. The apparatus of claim 13 , wherein the one more tests further comprise one or more of a memory built-in self-test or a logic built-in self-test, or an at speed through-silicon-via (TSV) test.

21. The apparatus of claim 13 , wherein the means for generating the one or more thermal hot spots further comprises:
means for connecting the design-for-test structure, via a first connection chain, to a plurality of temperature sensors on the IC;
means for connecting the design-for-test structure, via a second chain, to a control register in each of the plurality of core blocks on the IC;
means for transmitting a first instruction, via the design-for-test structure, to at least one core block on the IC to trigger operation of the core block; and
means for transmitting a second instruction, via the design-for-test structure, to periodically check the temperature of one or more of the plurality of temperature sensors until a desired temperature is reached.

22. The apparatus of claim 21 , wherein the means for triggering operation of the core block comprises means for feeding one or more structural vectors into the core block to trigger its operation.

23. The apparatus of claim 22 , wherein the structural vectors are fed into the core block via external automated test equipment.

24. The apparatus of claim 22 , wherein the structural vectors are generated on the IC.

25. An apparatus for testing integrated circuit (IC) performance, comprising:
at least one processor configured to:
generate, via a design-for-test structure on the IC, one or more thermal hot spots in one or more core blocks of the IC based on a received thermal profile, wherein the at least one processor is configured to generate the one or more thermal hot spots in one or more core blocks by exciting at least one core block of the IC by using test vectors that mimic a functional operation of the at least one core block; and
initiate one or more through-silicon-via (TSV) tests on one or more components of the IC over a range of voltage and frequency values when at least one of the one or more thermal hot spots is present; and
a memory cou

Assignees

• Qualcomm Inc

Inventors

• Chakraborty Tapan J
• Sethuram Rajamani
• Radojcic Ratibor

Classifications

• G01R31/2874 Primary

  related to temperature · CPC title

• G01R31/2875 Primary

  related to heating · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title