Method for forming a semiconductor structure having a porous semiconductor layer in RF devices
US-12347673-B2 · Jul 1, 2025 · US
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Racanelli Marco patents
Racanelli Marco is listed as an inventor on 16 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Racanelli Marco |
| Total patents | 16 |
| First publication | Aug 11, 2015 |
| Latest publication | Jul 1, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Semiconductor structure having porous semiconductor segment for RF devices and bulk semiconductor region for non-RF devices
US-11195920-B2 · Dec 7, 2021 · US
Method for Forming a Semiconductor Structure Having a Porous Semiconductor Layer in RF Devices
US-2021375618-A1 · Dec 2, 2021 · US
Semiconductor structure having porous semiconductor layer for RF devices
US-11164740-B2 · Nov 2, 2021 · US
High performance SiGe heterojunction bipolar transistors built on thin-film silicon-on-insulator substrates for radio frequency applications
US-10991631-B2 · Apr 27, 2021 · US
Semiconductor Structure Having Porous Semiconductor Segment for RF Devices and Bulk Semiconductor Region for Non-RF Devices
US-2021111249-A1 · Apr 15, 2021 · US
Semiconductor Structure Having Porous Semiconductor Layer for RF Devices
US-2021111019-A1 · Apr 15, 2021 · US
High performance SiGe heterojunction bipolar transistors built on thin film silicon-on-insulator substrates for radio frequency applications
US-10622262-B2 · Apr 14, 2020 · US
Bulk CMOS RF switch with reduced parasitic capacitance
US-10177044-B2 · Jan 8, 2019 · US
Bulk CMOS RF switch with reduced parasitic capacitance
US-10177045-B2 · Jan 8, 2019 · US
Recent patents
Latest publications not already listed above.
Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology
US-9941353-B2 · Apr 10, 2018 · US
Structure and Method for Mitigating Substrate Parasitics in Bulk High Resistivity Substrate Technology
US-2017338305-A1 · Nov 23, 2017 · US
Isolated through silicon via and isolated deep silicon via having total or partial isolation
US-9673081-B2 · Jun 6, 2017 · US
Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication
US-9412758-B2 · Aug 9, 2016 · US
Deep N wells in triple well structures
US-9136157-B1 · Sep 15, 2015 · US
Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation
US-9105681-B2 · Aug 11, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Newport Fab Llc | 12 |
| Newport Fab Llc Dba Jazz Semiconductor | 4 |
| Racanelli Marco | 2 |
| Zwingman Robert L | 1 |
| Kar-Roy Arjun | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W44/20 | 8 |
| H10W10/17 | 8 |
| H10W10/014 | 8 |
| H01L23/66 | 8 |
| H10W10/181 | 7 |