High performance SiGe heterojunction bipolar transistors built on thin-film silicon-on-insulator substrates for radio frequency applications

Patent metadata

Field	Value
Publication number	US-10991631-B2
Application number	US-201816026006-A
Country	US
Kind code	B2
Filing date	Jul 2, 2018
Priority date	Oct 6, 2017
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

First claim

We claim:

1. A method of fabricating a silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) on the same semiconductor substrate, the method comprising:
forming a first silicon region and a second silicon region over a dielectric layer formed over the semiconductor substrate;
forming one or more shallow trench isolation regions through the first and second silicon regions, wherein all of the one or more shallow trench isolation regions extend entirely through the first and second silicon regions;
fabricating a SOI CMOS transistor in the first silicon region; and
fabricating a collector region of the SOI HBT in the second silicon region by:
performing a first implant to introduce an impurity of a first conductivity type into a local collector region in the second silicon region; and
performing a second implant to introduce an impurity of the first conductivity type into an extrinsic collector region in the second silicon region, wherein the extrinsic collector region is separated from, and is not continuous with, the local collector region within the second silicon region, and wherein the local collector region is more heavily doped than the extrinsic collector region.

2. The method of claim 1 , further comprising forming an emitter structure over the local collector region.

3. The method of claim 1 , wherein fabricating the collector region further comprises performing a third implant to introduce an impurity of the first conductivity type into the entire second silicon region, including a sub-collector region located between the local collector region and the extrinsic collector region in the second silicon region.

4. A method of fabricating a silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) on the same semiconductor substrate, the method comprising:
forming a first silicon region and a second silicon region over a dielectric layer formed over the semiconductor substrate;
fabricating a SOI CMOS transistor in the first silicon region; and
fabricating a collector region of the SOI HBT in the second silicon region by:
performing a first implant to introduce an impurity of a first conductivity type into a local collector region in the second silicon region; and
performing a second implant to introduce an impurity of the first conductivity type into an extrinsic collector region in the second silicon region, wherein the extrinsic collector region is separated from, and is not continuous with, the local collector region within the second silicon region, wherein the first implant also introduces an impurity of the first conductivity type into a collector contact region, separate from the local collector region, and continuous with the extrinsic collector region.

5. The method of claim 4 , wherein the second implant also introduces an impurity of the first conductivity type into the collector contact region.

6. A method of fabricating a silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) on the same semiconductor substrate, the method comprising:
forming a first silicon region and a second silicon region over a dielectric layer formed over the semiconductor substrate;
fabricating a SOI CMOS transistor in the first silicon region; and
fabricating a collector region of the SOI HBT in the second silicon region by:
performing a first implant to introduce an impurity of a first conductivity type into a local collector region in the second silicon region; and
performing a second implant to introduce an impurity of the first conductivity type into an extrinsic collector region in the second silicon region, wherein the extrinsic collector region is separated from, and is not continuous with, the local collector region within the second silicon region;

forming a dielectric spacer layer over the first silicon region and the second silicon region; and
etching a portion of the dielectric spacer layer to expose the local collector region and a first portion of the extrinsic collector region, wherein the etched dielectric spacer layer extends over a second portion of the extrinsic collector region.

7. The method of claim 6 , further comprising forming a silicon germanium (SiGe) layer over the etched dielectric spacer layer, the local collector region and the extrinsic collector region.

8. The method of claim 7 , further comprising doping the SiGe layer to a second conductivity type, opposite the first conductivity type.

9. The method of claim 7 , further comprising forming an emitter on the SiGe layer over the local collector region.

10. The method of claim 9 , further comprising:
forming a mask over the SiGe layer and the emitter;
etching the SiGe layer through the mask to form a SiGe base structure; and
etching the dielectric spacer layer through the mask, wherein a portion of the dielectric spacer layer remains over the extrinsic collector region.

11. The method of claim 10 , wherein second portions of the dielectric spacer layer remain adjacent to a gate electrode of the SOI CMOS transistor.

12. The method of claim 7 , further comprising:
forming a mask over the SiGe layer, wherein the mask covers the local collector region and a first portion of the extrinsic collector region;
etching the SiGe layer through the mask to form a SiGe base structure; and
etching the dielectric spacer layer through the mask, wherein a portion of the dielectric spacer layer remains over the second portion of the extrinsic collector region.

13. A method of fabricating a silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) on the same semiconductor substrate, the method comprising:
forming a first silicon region and a second silicon region over a dielectric layer formed over the semiconductor substrate;
fabricating a SOI CMOS transistor in the first silicon region; and
fabricating a collector region of the SOI HBT in the second silicon region by:
performing a first implant to introduce an impurity of a first conductivity type into a local collector region in the second silicon region; and
performing a second implant to introduce an impurity of the first conductivity type into an extrinsic collector region in the second silicon region, wherein the extrinsic collector region is separated from, and is not continuous with, the local collector region within the second silicon region, wherein the local collector region is more heavily doped than the extrinsic collector region, and wherein the local collector region and the extrinsic collector region extend entirely through the second silicon region.

14. The method of claim 1 , wherein the local collector region is separated from the extrinsic collector region by a subcollector region within the second silicon region.

15. The method of claim 14 , wherein the subcollector region has the first conductivity type, wherein a dopant concentration of the subcollector region is lower than a dopant concentration of the local collector region and a dopant concentration of the extrinsic collector region.

16. The method of claim 14 , wherein the local collector region, the extrinsic collector region and the subcollector region extend entirely through the second silicon region.

17. The method of claim 1 , wherein the first and second silicon region have the same thickness.

18. The method of claim 1 , further comprising preventing the first implant and the second implant from introducing impurities into a subcollector region located between the local collector region and

Assignees

• Newport Fab Llc

Inventors

• Preisler Edward J
• Hurwitz Paul D
• Racanelli Marco
• Howard David J

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D84/0109

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title