Method for forming a semiconductor structure having a porous semiconductor layer in RF devices

Patent metadata

Field	Value
Publication number	US-12347673-B2
Application number	US-202117400712-A
Country	US
Kind code	B2
Filing date	Aug 12, 2021
Priority date	Oct 9, 2019
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor structure comprising:
forming a single-layer crystalline epitaxial layer directly over a non-sacrificial porous semiconductor layer, said non-sacrificial porous semiconductor layer being situated over a substrate;
forming an electrical isolation region terminating partway through said non-sacrificial porous semiconductor layer;
forming a first semiconductor device in said single-layer crystalline epitaxial layer;
completing said manufacturing of said semiconductor structure such that said non-sacrificial porous semiconductor layer and said substrate remain in said semiconductor structure upon said completing;
said substrate having a first dielectric constant, and said non-sacrificial porous semiconductor layer having a second dielectric constant that is substantially less than said first dielectric constant such that said non-sacrificial porous semiconductor layer reduces signal leakage from said first semiconductor device.

2. The method of claim 1 , further comprising annealing said non-sacrificial porous semiconductor layer prior to said forming said single-layer crystalline epitaxial layer.

3. The method of claim 1 , wherein said electrical isolation region extends through said single-layer crystalline epitaxial layer.

4. The method of claim 1 , wherein said forming said electrical isolation region comprises etching into said non-sacrificial porous semiconductor layer.

5. The method of claim 1 , further comprising forming a second semiconductor device in said single-layer crystalline epitaxial layer, wherein said electrical isolation region separates said first and second semiconductor devices.

6. The method of claim 1 , wherein said non-sacrificial porous semiconductor layer is porous silicon.

7. The method of claim 1 , wherein said first semiconductor device is a transistor, and a depth of a source/drain junction of said transistor is substantially less than a thickness of said single-layer crystalline epitaxial layer, such that said source/drain junction is not in contact with said non-sacrificial porous semiconductor layer.

8. The method of claim 1 , wherein said first semiconductor device is a transistor, and a depth of a source/drain junction of said transistor is substantially equal to a thickness of said single-layer crystalline epitaxial layer, such that said source/drain junction is in contact with said non-sacrificial porous semiconductor layer.

9. A method for manufacturing a semiconductor structure comprising:
forming a non-sacrificial porous silicon layer over a substrate;
forming a single-layer crystalline epitaxial layer directly over said non-sacrificial porous silicon layer;
forming an electrical isolation region terminating partway through said non-sacrificial porous silicon layer;
forming first and second transistors in said single-layer crystalline epitaxial layer, wherein said electrical isolation region separates said first and second transistors;
completing said manufacturing of said semiconductor structure such that said non-sacrificial porous silicon layer and said substrate remain in said semiconductor structure upon said completing.

10. The method of claim 9 , wherein said forming said electrical isolation region comprises etching into said non-sacrificial porous silicon layer.

11. The method of claim 9 , wherein said electrical isolation region extends through said single-layer crystalline epitaxial layer.

12. The method of claim 9 , wherein a depth of a source/drain junction of said first transistor is substantially less than a thickness of said single-layer crystalline epitaxial layer, such that said source/drain junction is not in contact with said non-sacrificial porous silicon layer.

13. The method of claim 9 , wherein a depth of a source/drain junction of said first transistor is substantially equal to a thickness of single-layer crystalline epitaxial layer, such that said source/drain junction is in contact with said non-sacrificial porous silicon layer.

14. A method for manufacturing a semiconductor structure comprising:
forming a non-sacrificial porous semiconductor layer over a substrate, said non-sacrificial porous semiconductor layer having a higher resistivity than said substrate;
forming a single-layer crystalline epitaxial layer directly over said non-sacrificial porous semiconductor layer;
forming an electrical isolation region terminating partway through said non-sacrificial porous semiconductor layer;
forming a first semiconductor device in said single-layer crystalline epitaxial layer;
completing said manufacturing of said semiconductor structure such that said non-sacrificial porous semiconductor layer and said substrate remain in said semiconductor structure upon said completing.

15. The method of claim 14 , wherein said substrate comprises a first semiconductor material, and said non-sacrificial porous semiconductor layer comprises said first semiconductor material.

16. The method of claim 14 , wherein said substrate comprises a first semiconductor material, and said non-sacrificial porous semiconductor layer comprises a second semiconductor material.

17. The method of claim 14 , further comprising forming a second semiconductor device in said single-layer crystalline epitaxial layer, wherein said electrical isolation region separates said first and second semiconductor devices.

18. The method of claim 17 , wherein said forming said electrical isolation region comprises etching into said non-sacrificial porous semiconductor layer.

19. The method of claim 17 , wherein said non-sacrificial porous semiconductor layer is porous silicon.

20. The method of claim 14 , wherein said first semiconductor device is a transistor, and a depth of a source/drain junction of said transistor is substantially less than a thickness of said single-layer crystalline epitaxial layer, such that said source/drain junction is not in contact with said non-sacrificial porous semiconductor layer.

Assignees

• Newport Fab Llc

Inventors

• Hurwitz Paul D
• Preisler Edward
• Howard David J
• Racanelli Marco

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/018

  using selective deposition of crystalline silicon, e.g. using epitaxial growth of silicon · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title