Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication

Patent metadata

Field	Value
Publication number	US-9412758-B2
Application number	US-28647108-A
Country	US
Kind code	B2
Filing date	Sep 29, 2008
Priority date	Dec 10, 2007
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the buried oxide layer, thereby causing the source/drain junction to have a source/drain junction capacitance. The SOI structure also comprises at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thereby electrically isolating the at least one transistor. In one embodiment the at least one trench is formed after fabrication of the at least one transistor and is filled with only dielectric. In one embodiment, one or more wells may be formed in the device layer. In one embodiment the bulk semiconductor layer has a high resistivity of typically about 1000 ohms-centimeter or greater.

First claim

The invention claimed is:

1. A semiconductor on insulator (SOI) structure comprising:
a buried oxide layer over a bulk semiconductor layer;
a device layer on said buried oxide layer, wherein said device layer comprises a substantially un-doped semiconductor at an interface between said device layer and said buried oxide layer;
at least one transistor fabricated in said device layer, wherein a source/drain junction of said at least one transistor does not contact said buried oxide layer, thereby forming a source/drain junction capacitance, and wherein a thickness of said device layer is configured such that said source/drain junction capacitance behaves substantially similarly to a source/drain junction capacitance of a semiconductor structure fabricated on a bulk silicon wafer;
at least one trench extending through said device layer and contacting a top surface of said buried oxide layer, thereby electrically isolating said at least one transistor;
wherein a high resistivity of said bulk semiconductor layer facilitates formation of at least one thick depletion region that extends from a bottom surface of said buried oxide layer into said bulk semiconductor layer, such that a thickness of said at least one thick depletion region is based on said high resistivity.

2. The SOI structure of claim 1 , wherein said at least one trench is formed after fabrication of said at least one transistor.

3. The SOI structure of claim 1 , wherein said at least one transistor is situated within an isolated island in said device layer.

4. The SOI structure of claim 1 , wherein said at least one transistor is an NFET.

5. The SOI structure of claim 1 , wherein said at least one transistor is a PFET.

6. The SOI structure of claim 1 , wherein said device layer comprises silicon.

7. The SOI structure of claim 1 , wherein said buried oxide layer comprises silicon oxide.

8. The SOI structure of claim 1 , wherein said bulk semiconductor layer comprises silicon.

9. The SOI structure of claim 1 further including a well formed in said device layer.

10. The SOI structure of claim 1 , wherein said high resistivity of said bulk semiconductor layer is approximately 1000 ohms-centimeter or greater.

11. A method for fabricating a semiconductor on insulator (SOI) structure, said method comprising:
forming a source/drain junction in a device layer situated on said buried oxide layer and over a bulk semiconductor layer such that said source/drain junction does not contact said buried oxide layer, thereby causing said source/drain junction to have a junction capacitance, wherein said device layer comprises a substantially un-doped semiconductor at an interface between said device layer and said buried oxide layer, and wherein a thickness of said device layer is configured such that said source/drain junction capacitance behaves substantially similarly to a source/drain junction capacitance of a semiconductor structure fabricated on a bulk silicon wafer;
utilizing said source/drain junction in formation of at least one transistor in said device layer;
wherein a high resistivity of said bulk semiconductor layer facilitates formation of at least one thick depletion region that extends from a bottom surface of said buried oxide layer into said bulk semiconductor layer, such that a thickness of said at least one thick depletion region is based on said high resistivity.

12. The method of claim 11 further comprising forming at least one trench in said device layer adjacent to said at least one transistor.

13. The method of claim 12 further comprising depositing a dielectric in said at least one trench, thereby electrically isolating said at least one transistor.

14. The method of claim 13 , wherein said depositing comprises completely filling said at least one trench with said dielectric.

Assignees

• Zwingman Robert L
• Racanelli Marco
• Newport Fab Llc

Inventors

• Zwingman Robert L
• Racanelli Marco

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D86/201 Primary

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title