Semiconductor structure having porous semiconductor layer for RF devices

Patent metadata

Field	Value
Publication number	US-11164740-B2
Application number	US-201916597779-A
Country	US
Kind code	B2
Filing date	Oct 9, 2019
Priority date	Oct 9, 2019
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a substrate having a first dielectric constant;
a porous semiconductor layer situated over said substrate;
at least one crystalline epitaxial layer situated directly on said porous semiconductor layer;
a first semiconductor device situated in said at least one crystalline epitaxial layer;
said porous semiconductor layer having a second dielectric constant that is substantially less than said first dielectric constant such that said porous semiconductor layer reduces signal leakage from said first semiconductor device.

2. The semiconductor structure of claim 1 , further comprising:
a second semiconductor device situated in said at least one crystalline epitaxial layer; and
an electrical isolation region separating said first and second semiconductor devices.

3. The semiconductor structure of claim 2 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.

4. The semiconductor structure of claim 1 , wherein said first semiconductor device is a transistor utilized in a radio frequency (RF) switch.

5. The semiconductor structure of claim 4 , wherein a depth of a source/drain junction of said transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous semiconductor layer.

6. The semiconductor structure of claim 4 , wherein a depth of a source/drain junction of said transistor is substantially equal to a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is in contact with said porous semiconductor layer.

7. The semiconductor structure of claim 1 , wherein said substrate comprises a first semiconductor material, and said porous semiconductor layer comprises a semiconductor material selected from one of said first semiconductor material and a second semiconductor material.

8. A semiconductor structure comprising:
a porous silicon layer;
at least one crystalline epitaxial layer situated directly on said porous silicon layer;
first and second transistors situated in said at least one crystalline epitaxial layer;
an electrical isolation region separating said first and second transistors.

9. The semiconductor structure of claim 8 , wherein said porous silicon layer is situated over a bulk silicon substrate.

10. The semiconductor structure of claim 8 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.

11. The semiconductor structure of claim 8 , wherein said first transistor is utilized in a radio frequency (RF) switch.

12. The semiconductor structure of claim 8 , wherein a depth of a source/drain junction of said first transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous silicon layer.

13. The semiconductor structure of claim 8 , wherein a depth of a source/drain junction of said first transistor is substantially equal to a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is in contact with said porous silicon layer.

14. A semiconductor structure comprising:
a porous semiconductor layer situated over a substrate, said porous semiconductor layer having a higher resistivity than said substrate;
at least one crystalline epitaxial layer situated directly on said porous semiconductor layer;
a first semiconductor device situated in said at least one crystalline epitaxial layer.

15. The semiconductor structure of claim 14 , wherein said substrate comprises a first semiconductor material, and said porous semiconductor layer comprises said first semiconductor material.

16. The semiconductor structure of claim 14 , wherein said substrate comprises a first semiconductor material, and said porous semiconductor layer comprises a second semiconductor material.

17. The semiconductor structure of claim 14 , further comprising:
a second semiconductor device situated in said at least one crystalline epitaxial layer; and
an electrical isolation region separating said first and second semiconductor devices.

18. The semiconductor structure of claim 17 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.

19. The semiconductor structure of claim 14 , wherein said first semiconductor device is a transistor utilized in a radio frequency (RF) switch.

20. The semiconductor structure of claim 19 , wherein a depth of a source/drain junction of said transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous semiconductor layer.

Assignees

• Newport Fab Llc

Inventors

• Hurwitz Paul D
• Preisler Edward
• Howard David J
• Racanelli Marco

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/018

  using selective deposition of crystalline silicon, e.g. using epitaxial growth of silicon · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title