Method for Forming a Semiconductor Structure Having a Porous Semiconductor Layer in RF Devices

Patent metadata

Field	Value
Publication number	US-2021375618-A1
Application number	US-202117400712-A
Country	US
Kind code	A1
Filing date	Aug 12, 2021
Priority date	Oct 9, 2019
Publication date	Dec 2, 2021
Grant date	—

Abstract

A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

First claim

1 - 13 . (canceled)

14 . A method comprising:
forming a crystalline epitaxial layer over a porous semiconductor layer, said porous semiconductor layer being situated over a substrate; forming a first semiconductor device in said crystalline epitaxial layer; said substrate having a first dielectric constant, and said porous semiconductor layer having a. second dielectric constant that is substantially less than said first dielectric constant such that said porous semiconductor layer reduces signal leakage from said first semiconductor device.

15 . The method of claim 14 , further comprising annealing said porous semiconductor layer prior to said forming said crystalline epitaxial layer.

16 . The method of claim 14 , further comprising forming an electrical isolation region at least in said crystalline epitaxial layer.

17 . The method of claim 16 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said crystalline epitaxial layer.

18 . The method of claim 16 , further comprising forming a second semiconductor device in said crystalline epitaxial layer, wherein said electrical isolation region separates said first and second semiconductor devices.

19 . The method of claim 14 , wherein said first semiconductor device is a transistor utilized in a radio frequency (RF) switch.

20 . The method of claim 19 , wherein a depth of a source/drain junction of said transistor is substantially less than a thickness of said crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous semiconductor layer.

21 . The method of claim 19 , wherein a depth of a source/drain junction of said transistor is substantially equal to a thickness of said crystalline epitaxial layer, such that said source/drain junction is in contact with said porous semiconductor layer.

22 . A method comprising:
forming at least one crystalline epitaxial layer over a porous silicon layer in a semiconductor structure; forming first and second transistors and an electrical isolation region separating said first and second transistors in said at least one crystalline epitaxial layer.

23 . The method of claim 22 , further comprising forming said porous silicon layer over a bulk silicon substrate prior to said forming said at least one crystalline epitaxial layer.

24 . The method of claim 22 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.

25 . The method of claim 22 , wherein a depth of a source/drain junction of said first transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous silicon layer.

26 . The method of claim 22 , wherein a depth of a source/drain junction of said first transistor is substantially equal to a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is in contact with said porous silicon layer.

27 . A method comprising:
forming a porous semiconductor layer over a substrate, said porous semiconductor layer having a higher resistivity than said substrate; forming at least one crystalline epitaxial layer over said porous semiconductor layer; forming a first semiconductor device in said at least one crystalline epitaxial layer.

28 . The method of claim 27 , wherein said substrate comprises a first semiconductor material, and said porous semiconductor layer comprises said first semiconductor material.

29 . The method of claim 27 , wherein said substrate comprises a first semiconductor material, and said porous semiconductor layer comprises a second semiconductor material.

30 . The method of claim 27 , further comprising forming a second semiconductor device and an electrical isolation region separating said first and second semiconductor devices in said at least one crystalline epitaxial layer.

31 . The method of claim 30 , wherein a depth of said electrical isolation region is equal to or greater than a thickness of said at least one crystalline epitaxial layer.

32 . The method of claim 27 , wherein said first semiconductor device is a transistor utilized in a radio frequency (RF) switch.

33 . The method of claim 32 , wherein a depth of a source/drain junction of said transistor is substantially less than a thickness of said at least one crystalline epitaxial layer, such that said source/drain junction is not in contact with said porous semiconductor layer.

Assignees

• Newport Fab Llc Dba Jazz Semiconductor

Inventors

• Hurwitz Paul D
• Preisler Edward
• Howard David J
• Racanelli Marco

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/018

  using selective deposition of crystalline silicon, e.g. using epitaxial growth of silicon · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title