On-package accelerator complex (AC) for integrating accelerator and IOS for scalable ran and edge cloud solution
US-12554667-B2 · Feb 17, 2026 · US
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Pal Rahul patents
Pal Rahul is listed as an inventor on 37 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Pal Rahul |
| Total patents | 37 |
| First publication | Mar 19, 2015 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Atomic handling for disaggregated 3d structured socs
US-2026017202-A1 · Jan 15, 2026 · US
Atomic handling for disaggregated 3D structured SoCs
US-12373348-B2 · Jul 29, 2025 · US
Three-dimensional stacked programmable logic fabric and processor design architecture
US-12294368-B2 · May 6, 2025 · US
Device, method and system for communicating between networked agents via a credit management bus
US-2025110813-A1 · Apr 3, 2025 · US
Accelerator controller hub
US-12229069-B2 · Feb 18, 2025 · US
Peer-to-peer link sharing for upstream communications from XPUS to a host processor
US-12197374-B2 · Jan 14, 2025 · US
Circuits And Methods For Multi-Layered Networks
US-2024031308-A1 · Jan 25, 2024 · US
Techniques to share memory across nodes in a system
US-2023236995-A1 · Jul 27, 2023 · US
Atomic handling for disaggregated 3d structured socs
US-2023114164-A1 · Apr 13, 2023 · US
Recent patents
Latest publications not already listed above.
Redundant cache-coherent memory fabric
US-11604730-B2 · Mar 14, 2023 · US
On-package accelerator complex (ac) for integrating accelerator and ios for scalable ran and edge cloud solution
US-2022222194-A1 · Jul 14, 2022 · US
Peer-to-peer link sharing for upstream communications from xpus to a host processor
US-2021318980-A1 · Oct 14, 2021 · US
Redundant cache-coherent memory fabric
US-2021200678-A1 · Jul 1, 2021 · US
Hardware lockstep checking within a fault detection interval in a system on chip
US-10831628-B2 · Nov 10, 2020 · US
Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles
US-10776309-B2 · Sep 15, 2020 · US
Misprediction-triggered local history-based branch prediction
US-10579414-B2 · Mar 3, 2020 · US
Mission-critical computing architecture
US-10514990-B2 · Dec 24, 2019 · US
Dynamic detection and prediction for store-dependent branches
US-10430198-B2 · Oct 1, 2019 · US
Branch predictor with empirical branch bias override
US-10423422-B2 · Sep 24, 2019 · US
Dynamic detection and prediction for store-dependent branches
US-2019220284-A1 · Jul 18, 2019 · US
Mission-critical computing architecture
US-2019163583-A1 · May 30, 2019 · US
Hardware lockstep checking within a fault detection interval in a system on chip
US-2019114243-A1 · Apr 18, 2019 · US
Method and apparatus for branch prediction utilizing primary and secondary branch predictors
US-2018349144-A1 · Dec 6, 2018 · US
Misprediction-triggered local history-based branch prediction
US-2018285115-A1 · Oct 4, 2018 · US
Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles
US-2018189232-A1 · Jul 5, 2018 · US
Branch Predictor with Empirical Branch Bias Override
US-2018173533-A1 · Jun 21, 2018 · US
Changing cache ownership in clustered multiprocessor
US-9940238-B2 · Apr 10, 2018 · US
Method, apparatus and system to send transactions without tracking
US-2017269959-A1 · Sep 21, 2017 · US
Changing cache ownership in clustered multiprocessor
US-2017255553-A1 · Sep 7, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 37 |
| Arora Manoj K | 1 |
| Blankenship Robert G | 1 |
| Pal Rahul | 1 |
| Nagaraj Dheemanth | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0831 | 11 |
| G06F12/0815 | 10 |
| G06F12/084 | 9 |
| G06F9/3848 | 7 |
| G06F13/1668 | 6 |