Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles

Patent metadata

Field	Value
Publication number	US-2018189232-A1
Application number	US-201615396522-A
Country	US
Kind code	A1
Filing date	Dec 31, 2016
Priority date	Dec 31, 2016
Publication date	Jul 5, 2018
Grant date	—

Abstract

A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with different tile sizes and wire densities operating and different bandwidths. A split merge switch is utilized between the different parts of the hetero-mesh to enable the sending of packets from tiles in one area of the hetero-mesh to another area of the hetero-mesh while employing a single end to end communication protocol.

First claim

What is claimed is:

1 . A method comprising:
receiving a packet to inject to a mesh interconnect by a component of a tile of a multi-core processor having a hetero-mesh topology; and injecting the packet to the mesh interconnect where a current cycle of the mesh interconnect corresponds to a cycle of a split merge switch (SMS) that enables the packet to traverse the SMS to a region of the hetero-mesh topology than the region of the tile.

2 . The method of claim 1 , further comprising:
determining whether a current slot of the mesh interconnect is empty.

3 . The method of claim 2 , further comprising:
waiting to a next cycle, where the current slot of the mesh interconnect is not empty.

4 . The method of claim 1 , further comprising:
determining whether the packet must traverse the SMS.

5 . The method of claim 1 , further comprising:
determining whether the packet is bounceable at a destination of the packet; and determining whether the packet will traverse the SMS upon bouncing at the destination.

6 . A method comprising:
receiving a packet to inject to a mesh interconnect by a component of a tile of a multi-core processor having a hetero-mesh topology; and injecting the packet to the mesh interconnect where a current cycle of the mesh interconnect corresponds to a cycle of a split merge switch (SMS) that enables the packet to traverse the SMS to link of a split link group corresponding to a destination of the packet into a denser region of the hetero-mesh topology than the region of the tile.

7 . The method of claim 6 , further comprising:
determining whether a current slot of the mesh interconnect is empty.

8 . The method of claim 7 , further comprising:
waiting to a next cycle, where the current slot of the mesh interconnect is not empty.

9 . The method of claim 6 , further comprising:
determining whether the packet is bounceable at a destination of the packet.

10 . The method of claim 6 , further comprising:
determining whether the packet will traverse the SMS upon bouncing at the destination.

11 . An apparatus comprising:
a core processor to process instructions and data; and an agent coupled to the core processor, the agent to enable communication with the core processor via a mesh interconnect, the agent to determine a cycle to inject outbound packets to the mesh interconnect, where a cycle to inject the packet is selected where the cycle of the mesh interconnect corresponds to a cycle of a split merge switch (SMS) that enables the packet to traverse the SMS to a sparser region of a hetero-mesh topology than the region of the core processor.

12 . The apparatus of claim 11 , wherein the agent to determine whether a current slot of the mesh interconnect is empty before injecting the packet.

13 . The apparatus of claim 12 , wherein the agent to wait to a next cycle, where the current slot of the mesh interconnect is not empty before injecting the packet.

14 . The apparatus of claim 12 , wherein the agent to determine whether the packet must traverse the SMS.

15 . The apparatus of claim 11 , wherein the agent to determine whether the packet will traverse the SMS upon bouncing at a destination.

16 . An apparatus comprising:
a core processor to process instructions and data; and an agent coupled to the core processor, the agent to enable communication with the core processor via a mesh interconnect, the agent to receive a packet to inject to the mesh interconnect, and determine a cycle to inject the packet to the mesh interconnect where the cycle of the mesh interconnect corresponds to a cycle of a split merge switch (SMS) that enables the packet to traverse the SMS to link of a split link group corresponding to a destination of the packet into a denser region of a hetero-mesh topology than the region of the core processor.

17 . The apparatus of claim 16 , wherein the agent to determine a next cycle, where a current slot of the mesh interconnect is not empty in which to inject the packet.

18 . The apparatus of claim 16 , wherein the agent determines an SMS arrival cycle according to a round robin scheme of the SMS.

19 . The apparatus of claim 16 , wherein the agent to determine whether the packet is bounceable at a destination of the packet.

20 . The apparatus of claim 16 , wherein the agent to determine whether the packet will traverse the SMS upon bouncing at the destination.

Assignees

• Intel Corp

Inventors

• Pal Rahul
• Agarwal Ishwar

Classifications

• G06F15/17381 Primary

  Two dimensional, e.g. mesh, torus · CPC title

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title