Peer-to-peer link sharing for upstream communications from XPUS to a host processor

Patent metadata

Field	Value
Publication number	US-12197374-B2
Application number	US-202117359321-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.

First claim

What is claimed is:

1. A processor unit comprising:
a first controller to couple to a host processor unit over a first link;
a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host processor unit via a third link; and
circuitry to determine whether to send a cache coherent request to the host processor unit over the first link or over the second link via the second processor unit.

2. The processor unit of claim 1 , wherein the first link and the third link are each links according to a Compute Express Link protocol.

3. The processor unit of claim 1 , wherein the circuitry is to determine whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the first link.

4. The processor unit of claim 3 , wherein the circuitry is to determine the amount of available upstream bandwidth over the first link based on a number of link credits available.

5. The processor unit of claim 3 , wherein the circuitry is to determine the amount of available upstream bandwidth over the first link based on a raw upstream bandwidth metric.

6. The processor unit of claim 1 , wherein the circuitry is to determine whether to send the cache coherent request over the first link or over the second link based on an amount of available bandwidth over the second link.

7. The processor unit of claim 1 , wherein the circuitry is to determine whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the third link.

8. The processor unit of claim 7 , wherein the circuitry is to determine the amount of available upstream bandwidth over the third link based on a number of host-bound requests received by the processor unit from the second processor unit, wherein the processor unit is to send the host-bound requests to the host processor unit over the first link.

9. The processor unit of claim 1 , further comprising second circuitry to:
track memory requests received from the second processor unit for memory of the host processor unit; and
respond to snoop requests associated with such memory from the host processor unit.

10. The processor unit of claim 1 , wherein the processor unit and the second processor unit are each graphics processing units.

11. A method comprising:
communicating, by a first processor unit, with a host processor unit over a first link;
communicating, by the first processor unit, with a second processor unit over a second link, wherein the second processor unit is to couple to the host processor unit via a third link; and
determining whether to send a cache coherent request to the host processor unit over the first link or over the second link via the second processor unit.

12. The method of claim 11 , further comprising determining whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the first link.

13. The method of claim 11 , further comprising determining whether to send the cache coherent request over the first link or over the second link based on an amount of available bandwidth over the second link.

14. The method of claim 11 , further comprising determining whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the third link.

15. The method of claim 11 , further comprising:
tracking memory requests received from the second processor unit for memory of the host processor unit; and
responding to snoop requests associated with such memory from the host processor unit.

16. A system comprising:
a host processor unit; and
a plurality of processor units, a processor unit of the plurality of processor units coupled to the host processor unit via a first link and to other processor units of the plurality of processor units via a plurality of second links, the other processor units coupled to the host processor unit via a plurality of third links;
wherein the processor unit is to determine whether to send a cache coherent request to the host processor unit over the first link or over one of the second links via one of the other processor units.

17. The system of claim 16 , wherein the processor unit is to determine whether to send the cache coherent request over the first link or over one of the second links based on an amount of available upstream bandwidth over the first link.

18. The system of claim 16 , wherein the processor unit is to determine whether to send the cache coherent request over the first link or over one of the second links based on an amount of available upstream bandwidths over the second links.

19. The system of claim 16 , wherein the processor unit is to send a plurality of cache coherent requests to the host processor unit via a first plurality of the other processor units.

20. The system of claim 16 , wherein the processor unit is to:
track memory requests received from a second processor unit of the plurality of processor units, the memory requests for memory of the host processor unit; and
respond to snoop requests associated with such memory from the host processor unit.

Assignees

• Intel Corp

Inventors

• Pal Rahul
• Suthar Nayan Amrutlal
• Puffer David M
• Jagannathan Ashok

Classifications

• G06F12/0815

  Cache consistency protocols · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title