On-package accelerator complex (AC) for integrating accelerator and IOS for scalable ran and edge cloud solution

Patent metadata

Field	Value
Publication number	US-12554667-B2
Application number	US-202217711986-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Apr 1, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

First claim

What is claimed is:

1 . A package, comprising:
a central processing unit (CPU) having a plurality of cores and a plurality of caches and a first interconnect structure; an accelerator complex, coupled to the CPU via a first die-to-die, chiplet-to-chiplet, or chip-to-chip interconnect, comprising at least one die and including, a second interconnect structure; a plurality of intellectual property (IP) blocks; a plurality of input-output (IO) interfaces coupling the plurality of IP blocks to the second interconnect structure; and a shared memory coupled to the second interconnect structure, wherein the shared memory is shared among the plurality of IP blocks and the plurality of cores.

2 . The package of claim 1 , wherein the accelerator complex comprises:
an IP interface tile comprising a first die including circuitry for the shared memory; a plurality of IP block dies; and a respective die-to-die interconnect coupling respective IP block dies to the IP interface tile.

3 . The package of claim 2 , wherein the CPU comprises a second die coupled to the IP interface tile via a die-to-die interconnect, and wherein the package comprises a multi-die package.

4 . The package of claim 1 , wherein the CPU comprises a first integrated circuit (IC) chip and the accelerator complex comprises a second IC chip, the CPU is coupled to the accelerator complex via a chip-to-chip interconnect, and the package comprises a multi-chip package or multi-chip module.

5 . The package of claim 1 , wherein the plurality of IP blocks includes one or more hardware accelerators, and wherein the accelerator complex includes an interface controller configured to schedule utilization of the one or more hardware accelerators.

6 . The package of claim 1 , wherein the accelerator complex includes an interface controller that is configured to set up data movement actions for chaining of tasks across two or more IP blocks.

7 . The package of claim 1 , having circuitry and logic to transfer data between a CPU core and an IP block by:
performing a first data transfer under which data are written by the CPU core to a buffer in the shared memory; and performing a second data transfer under which the data that are written to the buffer in the shared memory are read by the IP block.

8 . The package of claim 1 , having circuitry and logic to transfer data between a first IP block and a second IP block by:
performing a first data transfer under which data are written by the first IP block to a buffer in the shared memory; and performing a second data transfer under which the data that are written to the buffer in the shared memory are read by the second IP block.

9 . The package of claim 1 , having circuitry and logic to transfer data between a first IP block and a second IP block by:
performing a first data transfer under which data are written by the first IP block to a buffer in the shared memory; and performing a second data transfer under which the data that are written to the buffer in the shared memory are written to a memory buffer in the second IP block.

10 . The package of claim 1 , wherein the accelerator complex further comprises a data mover comprising an IP block that provides software including host applications to be executed by the CPU with an interface for effecting data movement between the plurality of IP blocks and host application domains.

11 . A system comprising:
memory; a multi-die package, including: a first die or chiplet comprising a central processing unit (CPU) die having a plurality of cores, a plurality of caches and a first interconnect structure to which a memory controller is coupled, the memory controller coupled to the memory via one or more memory channels; a second die or chiplet comprising an Intellectual Property (IP) interface tile coupled to the CPU die via a die-to-die interconnect or a chiplet-to-chiplet interconnect, including, a second interconnect structure; a shared memory coupled to the second interconnect structure; and a plurality of IP interfaces coupled to the second interconnect structure; and a plurality of intellectual property (IP) blocks coupled to the second interconnect structure via a respective IP interface, a plurality of input output (IO) interfaces coupling the plurality of IP blocks to the second interconnect structure, wherein the shared memory is shared among the plurality of IP blocks and the plurality of cores.

12 . The system of claim 11 , wherein the plurality of IP blocks include one or more IP blocks that are integrated on separate dies that are coupled to the IP interface tile via respective die-to-die interconnects or chiplet-to-chiplet interconnects.

13 . The system of claim 11 , wherein the plurality of IP blocks includes one or more hardware accelerators, and wherein the IP interface tile includes an interface controller configured to schedule utilization of the one or more hardware accelerators.

14 . The system of claim 13 , wherein the interface controller is further configured to set up data movement actions for chaining of tasks across two or more IP blocks.

15 . The system of claim 11 , wherein the IP interface tile includes a data mover coupled to the second interconnect structure comprising an IP block that provides software including host applications to be executed by the CPU with an interface for effecting data movement between the plurality of IP blocks and host application domains.

16 . A method performed in a system including a multi-die package having a first die including a central processing unit (CPU) and a second die coupled to the first die comprising an Intellectual Property (IP) interface tile having an integrated memory and a plurality of IP interfaces coupled to a network interface and a plurality of accelerators, the method comprising:
receiving data at the network interface and writing the data to the integrated memory; and employing a pipeline chain of accelerator operations with at least two of the plurality of accelerators, the pipeline chain of accelerator operations including,
a first accelerator reading data from a buffer in the integrated memory, processing the data, and writing first processed data back to the integrated memory; and
a second accelerator reading the first processed data from the integrated memory, processing the first processed data to produce second processed data, and writing the second processed data back to the integrated memory.

17 . The method of claim 16 , wherein the system in is implemented in a Radio Access Network (RAN), and the method is used to process data received at a RAN facility.

18 . The method of claim 17 , wherein at least one of the first and second accelerators comprise an artificial intelligence (AI) accelerators.

19 . The method of claim 16 , wherein the IP interface tile includes an interface controller, further comprising setting up the pipeline chain of accelerator operations using the interface controller.

20 . The method of claim 16 , wherein at least two of the plurality of accelerator are implemented on separate dies that are coupled to respective IP interfaces in the IP interface tile via die-to-die interconnects or chiplet to chiplet interconnects.

Assignees

• Intel Corp

Inventors

• Chandwani Neelam
• Bendi Shridhar
• Vivekanandham Rajesh
• Pal Rahul
• Dahlen Eric J
• Hasbun Marin Antonio J
• Wang Chung-Chi
• Li Qian
• Nikopour Hosein
• Kota Venkata Sravanthi
• Poornachandran Rajesh
• Mukherjee Udayan

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G06F13/124

  where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine · CPC title

• G06F13/1663

  Access to shared memory · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title