Mission-critical computing architecture

Patent metadata

Field	Value
Publication number	US-10514990-B2
Application number	US-201715823313-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Nov 27, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

First claim

What is claimed is:

1. A coherent redundancy controller device, comprising:
flow control circuitry to receive operational requests from a requestor node, wherein the operational requests are to be processed by shared agents to produce corresponding responses;
request allocator circuitry coupled to the flow control circuitry and configured to duplicate a first request from among the operational requests to be redundantly processed independently and asynchronously by distinct ones of the shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response; and
response comparator circuitry coupled to the flow control circuitry and configured to compare the first redundant response against the second redundant response to produce a comparison result;
wherein in response to the comparison result being indicative of a match between a first redundant response and the second redundant response, the flow control circuitry is to merge the first redundant response and the second redundant response to produce a single final response to the first request to be read by the requestor node; and
wherein in response to the comparison result being indicative of a non-match between the first redundant response and the second redundant response, the flow control circuitry is to perform an exception response.

2. The coherent redundancy controller device of claim 1 , wherein the requestor node is a processor core.

3. The coherent redundancy controller device of claim 1 , wherein the requestor node is an input/output agent of a computer system.

4. The coherent redundancy controller device of claim 1 , wherein the operational requests include mission-critical requests and non-mission-critical requests, and wherein the flow control circuitry is to direct the mission-critical requests to the request allocator.

5. The coherent redundancy controller device of claim 4 , wherein the flow control circuitry is to cause the non-mission-critical requests to bypass the request allocator.

6. The coherent redundancy controller device of claim 4 , wherein the mission-critical requests are associated with a preconfigured set of addresses, and wherein the flow control circuitry is to direct the mission-critical requests to the request allocator based on a comparison of addressing associated with each of the mission-critical requests against the preconfigured set of addresses.

7. The coherent redundancy controller device of claim 1 , wherein the response comparator circuitry is to compute and store a first checksum of the first redundant response, and to compute a second checksum of the second redundant response and compare the first checksum against the second checksum to produce the comparison result.

8. The coherent redundancy controller device of claim 1 , wherein the flow control circuitry is to interface with the requestor node such that the requestor node is unaware of any redundant processing of the operational requests.

9. The coherent redundancy controller device of claim 1 , wherein the exception response includes suppressing the redundant counterpart responses from being accessed by the requestor node.

10. The coherent redundancy controller device of claim 1 , wherein the exception response includes an initial retry wherein the flow control circuitry is to cause the request allocator circuitry to duplicate the first request from among the operational requests to be redundantly processed independently and asynchronously by the same shared agents that were previously used to redundantly process the first request, to produce retried redundant counterpart responses including a first retried redundant response and a second retried redundant response to be compared against the first retried redundant response.

11. The coherent redundancy controller device of claim 10 , wherein in response to a non-match between the first retried redundant response and the second retried redundant response, the flow control circuitry is to cause the request allocator circuitry to perform a fault-isolation test wherein the first request is redundantly processed independently and asynchronously different ones of the shared agents that were not previously used to redundantly process the first request, to produce tested redundant counterpart responses including a first tested redundant response and a second tested redundant response to be compared against the first tested redundant response.

12. The coherent redundancy controller device of claim 1 , wherein the flow control circuitry, the request allocator circuitry, and the response comparator circuitry implement a transparent redundancy manager including a hardware-based super queue and a hardware-based snoop queue;
wherein the super queue is to store identifiers of operational requests and associated responses during redundant processing of those respective requests by the shared agents; and
wherein the snoop queue is to store snoop messages from the shared agents directed to the requestor node while those snoop messages are outstanding.

13. The coherent redundancy controller device of claim 1 , wherein the flow control circuitry, the request allocator circuitry, and the response comparator circuitry are integrated on a common integrated circuit with the requestor node.

14. The coherent redundancy controller device of claim 13 , wherein the shared agents are integrated on a common integrated circuit with the requestor node.

15. The coherent redundancy controller device of claim 1 , wherein the shared agents include a set of cache controllers.

16. A method of manufacturing a central processing unit (CPU) device, the method, comprising:
forming a processor core;
forming a plurality of shared agents;
forming flow control circuitry configured to receive operational requests from a the processor core, wherein the operational requests are to be processed by the shared agents to produce corresponding responses;
forming request allocator circuitry coupled to the flow control circuitry and configured to duplicate a first request from among the operational requests to be redundantly processed independently and asynchronously by distinct ones of the shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response; and
forming response comparator circuitry coupled to the flow control circuitry and configured to compare the first redundant response against the second redundant response to produce a comparison result;
wherein the flow control circuitry is configured such that:
in response to the comparison result being indicative of a match between a first redundant response and the second redundant response, the flow control circuitry is to merge the first redundant response and the second redundant response to produce a single final response to the first request to be read by the processor core; and
wherein in response to the comparison result being indicative of a non-match between the first redundant response and the second redundant response, the flow control circuitry is to perform an exception response.

17. The method of claim 16 , wherein the operational requests include mission-critical requests and non-mission-critical requests, and wherein the flow control circuitry is to direct the mission-critical requests to the request allocator.

18. The method of claim 16 , wherein forming the flow control circuitry includes interfacing the flow control circuitry with the processor core such that the processor core is unaware of any redundant processing

Assignees

• Intel Corp

Inventors

• Fahim Bahaa
• Choudhary Swadesh
• Pal Rahul
• Geetha Vedaraman

Classifications

• G06F9/3818

  Decoding for concurrent execution · CPC title

• G06F11/2017 Primary

  where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089) · CPC title

• G06F11/141

  for bus or memory accesses · CPC title

• G06F11/1608 Primary

  Error detection by comparing the output signals of redundant hardware (G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40) · CPC title

• G06F11/184

  where the redundant components implement processing functionality · CPC title