Methods and Systems for Inter-Pipeline Data Hazard Avoidance
US-2025390310-A1 · Dec 25, 2025 · US
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Nield Simon patents
Nield Simon is listed as an inventor on 59 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nield Simon |
| Total patents | 59 |
| First publication | Mar 29, 2018 |
| Latest publication | Dec 25, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Scheduling Tasks Using Swap Flags
US-2025348313-A1 · Nov 13, 2025 · US
Methods and systems for inter-pipeline data hazard avoidance
US-12405802-B2 · Sep 2, 2025 · US
Scheduling tasks using swap flags
US-12367046-B2 · Jul 22, 2025 · US
Sorting memory address requests for parallel memory access using input address match masks
US-2025156342-A1 · May 15, 2025 · US
Sorting memory address requests for parallel memory access using input address match masks
US-12298924-B2 · May 13, 2025 · US
Methods and systems for inter-pipeline data hazard avoidance
US-2025021340-A1 · Jan 16, 2025 · US
Scheduling tasks using targeted pipelines
US-2024311187-A1 · Sep 19, 2024 · US
Scheduling tasks using targeted pipelines
US-12020067-B2 · Jun 25, 2024 · US
Scheduling tasks using work fullness counter
US-2024160472-A1 · May 16, 2024 · US
Recent patents
Latest publications not already listed above.
Sorting memory address requests for parallel memory access using input address match masks
US-2024078194-A1 · Mar 7, 2024 · US
Methods and systems for inter-pipeline data hazard avoidance
US-11900122-B2 · Feb 13, 2024 · US
Scheduling tasks using work fullness counter
US-11868807-B2 · Jan 9, 2024 · US
Task Scheduling in a GPU Using Wakeup Event State Data
US-2023376348-A1 · Nov 23, 2023 · US
Sorting memory address requests for parallel memory access using input address match masks
US-11816044-B2 · Nov 14, 2023 · US
Methods and systems for inter-pipeline data hazard avoidance
US-2023350689-A1 · Nov 2, 2023 · US
Allocation of memory resources to simd workgroups
US-2023297425-A1 · Sep 21, 2023 · US
Task scheduling in a GPU using wakeup event state data
US-11720399-B2 · Aug 8, 2023 · US
Queues for inter-pipeline data hazard avoidance
US-11698790-B2 · Jul 11, 2023 · US
Allocation of memory resources to SIMD workgroups
US-11656908-B2 · May 23, 2023 · US
Scheduling tasks using swap flags
US-2023097760-A1 · Mar 30, 2023 · US
Scheduling tasks using swap flags
US-11531545-B2 · Dec 20, 2022 · US
Scheduling tasks using targeted pipelines
US-2022276895-A1 · Sep 1, 2022 · US
Data selection for a processor pipeline using multiple supply lines
US-11429389-B2 · Aug 30, 2022 · US
Scheduling tasks using targeted pipelines
US-11366691-B2 · Jun 21, 2022 · US
Sorting memory address requests for parallel memory access using input address match masks
US-2022156203-A1 · May 19, 2022 · US
Task Scheduling in a GPU Using Wakeup Event State Data
US-2022091885-A1 · Mar 24, 2022 · US
Scheduling tasks using work fullness counter
US-2022075652-A1 · Mar 10, 2022 · US
Queues for Inter-Pipeline Data Hazard Avoidance
US-2022066781-A1 · Mar 3, 2022 · US
Sorting memory address requests for parallel memory access using input address match masks
US-11249925-B2 · Feb 15, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Imagination Tech Ltd | 59 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/4881 | 35 |
| G06F9/3016 | 32 |
| G06F9/3867 | 29 |
| G06F7/575 | 25 |
| G06F9/3001 | 25 |