Allocation of memory resources to SIMD workgroups

Patent metadata

Field	Value
Publication number	US-11656908-B2
Application number	US-202117220849-A
Country	US
Kind code	B2
Filing date	Apr 1, 2021
Priority date	Sep 15, 2017
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.

First claim

What is claimed is:

1. A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units for processing SIMD tasks, the memory subsystem comprising:
a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor;
a translation unit configured to associate tasks with one or more physical addresses of the shared memory; and
a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a task, allocate to the task a contiguous virtual memory block and cause the translation unit to associate the task with a plurality of physical addresses of memory portions each corresponding to a region of the contiguous virtual memory block, said memory portions collectively embodying the complete contiguous virtual memory block, wherein the contiguous virtual memory block comprises a base address which is the physical address of one of the memory portions associated with the task.

2. The memory subsystem according to claim 1 , wherein at least some of the plurality of memory portions of the contiguous virtual memory block are not contiguous in the shared memory.

3. The memory subsystem according to claim 1 , wherein the translation unit is operable to subsequently service an access request received from the task in respect of the contiguous virtual memory block, the access request including an identifier of the task and an offset of an area of memory within the contiguous virtual memory block, the translation unit being configured to service the access request at the memory portion corresponding to the region of the contiguous virtual memory block indicated by the offset.

4. The memory subsystem according to claim 1 , wherein the translation unit comprises a content addressable memory configured to return one or more corresponding physical addresses in response to receiving an identifier of the item and an offset within the contiguous virtual memory block.

5. The memory subsystem according to claim 1 , wherein the SIMD processor is configured for processing one or more workgroups, each workgroup comprising a plurality of SIMD tasks, the task is the first-received task of a workgroup, and the resource allocator is configured to reserve for the workgroup sufficient memory portions for each task of the workgroup to receive memory resources equivalent to the first memory resources and to allocate to the first-received task the requested memory resources from the memory portions reserved for the workgroup.

6. The memory subsystem according to claim 5 , wherein the resource allocator is configured to allocate each task of the workgroup a contiguous virtual memory block such that the contiguous virtual memory blocks allocated to the tasks of the workgroup collectively represent a contiguous superblock of virtual memory blocks.

7. The memory subsystem according to claim 6 , wherein the resource allocator is configured to, in response to subsequently receiving a memory resource request in respect of a second task of the workgroup, allocate a contiguous virtual memory block from the contiguous superblock of virtual memory blocks to the second task.

8. The memory subsystem according to claim 5 , wherein the resource allocator may maintain a data structure identifying which of the one or more workgroups are currently allocated a contiguous virtual memory block.

9. The memory subsystem according to claim 8 , wherein the data structure comprises a fine status array arranged to indicate whether each memory portion of the shared memory is allocated to the task.

10. A method of allocating shared memory resources to tasks for execution in a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units each configured for processing SIMD tasks, the method comprising:
receiving a memory resource request for first memory resources in respect of a task;
allocating to the task a contiguous virtual memory block; and

associating the task with a plurality of physical addresses of memory portions of a shared memory, each corresponding to a region of the contiguous virtual memory block, said memory portions collectively embodying the complete contiguous virtual memory block, wherein the contiguous virtual memory block comprises a base address which is the physical address of one of the memory portions associated with the task.

11. The method according to claim 10 , wherein at least some of the plurality of memory portions of the contiguous virtual memory block are not contiguous in the shared memory.

12. The method according to claim 10 , further comprising:
subsequently receiving an access request received from the task in respect of the contiguous virtual memory block, the access request including an identifier of the task and an offset of an area of memory within the contiguous virtual memory block; and
servicing the access request by accessing the memory portion corresponding to the region of the contiguous virtual memory block indicated by the offset.

13. The method according to claim 10 , wherein tasks are grouped together in workgroups for execution at the SIMD processor, the task is the first-received task of a workgroup, and the allocating to the task a contiguous virtual memory block comprises:
reserving for the workgroup sufficient memory portions for each task of the workgroup to receive memory resources equivalent to the first memory resources; and
allocating to the first-received task the requested memory resources from the memory portions reserved for the workgroup.

14. The method according to claim 13 , wherein the reserving for the workgroup comprises reserving each task of the workgroup a contiguous virtual memory block such that the contiguous virtual memory blocks allocated to the tasks of the workgroup collectively represent a contiguous superblock of virtual memory blocks.

15. The method according to claim 14 , further comprising, in response to subsequently receiving a memory resource request in respect of a second task of the workgroup, allocating a contiguous virtual memory block from the contiguous superblock of virtual memory blocks to the second task.

16. The method according to claim 10 , further comprising maintaining a data structure identifying which of the one or more workgroups are currently allocated a contiguous virtual memory block.

17. The method according to claim 16 , wherein the data structure comprises a fine status array arranged to indicate whether each memory portion of the shared memory is allocated to the task.

18. The memory subsystem according to claim 1 , wherein the memory subsystem is embodied in hardware on an integrated circuit.

19. The method according to claim 10 , further comprising returning one or more corresponding physical addresses in response to receiving an identifier of the item and an offset within the contiguous virtual memory block.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units for processing SIMD tasks, the memory subsystem comprising:
a shared memory partitioned into a plurality of memory portions for allocation to tasks

Assignees

• Imagination Tech Ltd

Inventors

• Iuliano Luca
• Nield Simon
• Foo Yoong-Chert
• Mower Ollie
• Redshaw Jonathan

Classifications

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F9/5022

  Mechanisms to release resources · CPC title

• G06F9/5016 Primary

  the resource being the memory · CPC title