Scheduling tasks using targeted pipelines

Patent metadata

Field	Value
Publication number	US-12020067-B2
Application number	US-202217746862-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	Jun 16, 2017
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.

First claim

What is claimed is:

1. A method of scheduling instructions within a parallel processing unit, comprising:
decoding, in an instruction decoder, an instruction in a scheduled task for a targeted ALU (Arithmetic Logic Unit);
if the targeted ALU is identified as a primary instruction pipeline, determining whether the scheduled task is already associated with the primary instruction pipeline from data associated with the primary instruction pipeline and sending the decoded instruction to the primary instruction pipeline; and
if the targeted ALU is not identified as a primary instruction pipeline, sending the decoded instruction to the pipeline associated with the targeted ALU.

2. The method according to claim 1 , further comprising:
if the scheduled task is not already included in the data, determining if the data is full; and triggering the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state; and
if the scheduled task is not already included in the data and that the data is not full, adding the scheduled task to the data and sending the decoded instruction to the primary instruction pipeline.

3. The method according to claim 1 , further comprising:
if the targeted ALU is not a primary instruction pipeline, checking the data to determine whether the scheduled task is already included in the data; removing the scheduled task from the data; and sending the decoded instruction to the targeted ALU.

4. The method according to claim 1 , further comprising:
if the primary instruction pipeline is full; and if the data has changed from being full to not being full, triggering the scheduler to re-activate an oldest scheduled task waiting for the primary instruction pipeline by removing the oldest scheduled task from the waiting state.

5. The method according to claim 1 , further comprising:
if a particular scheduled task has been de-activated, checking if the particular scheduled task is included in the data and in response to determining that the particular scheduled task is included in the data, removing the particular scheduled task from the data associated with the primary instruction pipeline.

6. The method according to claim 1 , further comprising:
when a particular scheduled task completes, checking if the particular scheduled task is included in the data and in response to determining that the particular scheduled task is included in the data, removing the particular scheduled task from the data.

7. An instruction controller comprising:
an input for receiving an instruction in a scheduled task for a targeted ALU (Arithmetic Logic Unit);
an instruction decoder arranged to decode the received instruction;
a memory element arranged to store data associating scheduled tasks with a primary instruction pipeline in a parallel processing unit; and
hardware logic arranged to determine:
if the targeted ALU is identified as a primary instruction pipeline, whether the scheduled task is already associated with the primary instruction pipeline based on the data and to send the decoded instruction to the primary instruction pipeline; and
if the targeted ALU is not identified as a primary instruction pipeline, to send the decoded instruction to the pipeline associated with the targeted ALU.

8. The instruction controller according to claim 7 , wherein the data comprises the data associating the scheduled tasks with the primary instruction pipeline.

9. The instruction controller according to claim 8 , further comprising:
hardware logic arranged, if scheduled task is not already included in the data and if the data is full, to trigger de-activating hardware logic in the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a waiting state; and
if the scheduled task is not already included in the data and the data is not full, to add the scheduled task to the data and send the decoded instruction to the primary instruction pipeline.

10. The instruction controller according to claim 8 , further comprising:
hardware logic arranged, if the targeted ALU is not a primary instruction pipeline, to check the data to determine whether the scheduled task is already included in the data; and
if the scheduled task is already included in the data, remove the scheduled task from the data and send the decoded instruction to the targeted ALU.

11. The instruction controller according to claim 8 , further comprising:
hardware logic arranged, if the data is full and the data has changed from being full to not being full, to trigger the scheduler to re-activate an oldest scheduled task waiting for the primary instruction pipeline by removing the oldest scheduled task from the waiting state.

12. The instruction controller according to claim 8 , further comprising:
hardware logic arranged, if a particular scheduled task has been de-activated and if the particular scheduled task is included in the data, to remove the particular scheduled task from the data.

13. The instruction controller according to claim 8 , further comprising:
hardware logic arranged, if a particular scheduled task completes and the particular scheduled task is included in the data, to remove the particular scheduled task from the data.

14. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction controller, the instruction controller comprising:
an input for receiving an instruction in a scheduled task for a targeted ALU (Arithmetic Logic Unit);
an instruction decoder arranged to decode the received instruction;
a memory element arranged to store data associating scheduled tasks with a primary instruction pipeline in a parallel processing unit; and
hardware logic arranged to determine:
if the targeted ALU is identified as a primary instruction pipeline, whether the scheduled task is already associated with the primary instruction pipeline and to send the decoded instruction to the primary instruction pipeline based on the data; and
if the targeted ALU is not identified as a primary instruction pipeline, to send the decoded instruction to the pipeline associated with the targeted ALU.

15. The non-transitory computer readable storage medium according to claim 14 , wherein the data comprises the data associating the scheduled tasks with the primary instruction pipeline.

16. The non-transitory computer readable storage medium according to claim 15 , further comprising:
hardware logic arranged, if scheduled task is not already included in the data and if the data is full, to trigger de-activating hardware logic in the scheduler to de-activate the scheduled task by changing the scheduled task from the active state to a waiting state; and
if the scheduled task is not already included in the data and the data is not full, to add the scheduled task to the data and send the decoded instruction to the primary instruction pipeline.

17. The non-transitory computer readable storage medium according to claim 15 , further comprising:
hardware logic arranged, if the targeted ALU is not a primary instruction pipeline, to check the data to determine whether the scheduled task is already included in the data; and
if the scheduled task is already included in the data, remove the scheduled task from the data and send the decoded instruction to the targeted ALU.

18. The non

Assignees

• Imagination Tech Ltd

Inventors

• Nield Simon
• Foo Yoong-Chert
• De Grasse Adam
• Iuliano Luca

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title