Sorting memory address requests for parallel memory access using input address match masks

Patent metadata

Field	Value
Publication number	US-11816044-B2
Application number	US-202217588078-A
Country	US
Kind code	B2
Filing date	Jan 28, 2022
Priority date	Sep 22, 2017
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

First claim

What is claimed is:

1. An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses, the apparatus comprising:
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset; and
a monitoring unit configured to generate an output flag whose status indicates whether all addresses in the subset identified by the binary classification dataset have been output by output generating logic, the output generating logic being configured to generate an output containing an address in the identified subset of addresses.

2. The apparatus of claim 1 , wherein the output generating logic is configured to generate a further output containing at least one further address of the identified subset of addresses, using the set of N input addresses, in response to the output flag indicating that not all addresses in the identified subset of addresses have been output by the output generating logic.

3. The apparatus of claim 1 , wherein the comparator block is configured to perform a new comparison of a new set of N input memory addresses in response to the output flag indicating that all addresses in the identified subset of addresses have been output by the output generating logic.

4. The apparatus of claim 1 , wherein the monitoring unit is configured to determine the number of addresses in the identified subset of addresses that have been identified and output by the output generating logic.

5. The apparatus of claim 1 , further comprising a combination logic unit configured to receive bits of the binary classification dataset; and sort the bits into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

6. The apparatus of claim 5 , further comprising an additional combination logic unit, with each of the combination logic units configured to receive a subset of the bits of the binary classification dataset.

7. The apparatus of claim 1 , wherein the binary classification dataset comprises N bits, each bit corresponding to a respective input memory address, the value of each bit indicating whether or not the corresponding memory address forms part of the identified subset.

8. The apparatus of claim 1 , wherein each address in the set of input addresses is associated with a validity identifier indicating whether the address is valid or invalid.

9. The apparatus of claim 1 , wherein each address in the set of input addresses that is not in the identified subset is at least one of: an invalid address; or equal to one of the addresses in the identified subset.

10. The apparatus of claim 1 , wherein the set of input memory addresses contains N addresses, and the comparator block is configured to: perform the comparison of input addresses by comparing each address a i in the set of input memory addresses with each subsequent address a j in the set of input memory addresses.

11. The apparatus of claim 1 , wherein the set of input memory addresses contains N addresses, and the comparator block is configured to perform the comparison of input addresses by comparing each address a i in the set of input memory addresses with each previous address a j in the set of input memory address.

12. The apparatus of claim 10 , wherein the comparator block is configured to generate the binary classification dataset by associating a first bit value with each address a j that is determined to be both: a valid address and not equal to address a i , and to associate a second bit value to each address a j that is determined to be at least one of: an invalid address or equal to address a i , the comparator block being further configured to identify an address a j as invalid in response to determining that address a j is equal to address a i .

13. The apparatus of claim 11 , wherein the comparator block is configured to generate the binary classification dataset by associating a first bit value with each address a i that is both: a valid address and not equal to any address a j ; and to associate a second bit value to each address a i that is either: an invalid address or equal to at least one other address a j .

14. The apparatus of claim 1 , wherein the comparator block is further configured to generate from the comparison of input addresses a match mask indicating, for each input address, which of the other input addresses match that input address.

15. The apparatus of claim 14 , wherein the apparatus further comprises address matching logic configured to identify, using the match mask, each input address that matches the address in the identified subset of addresses that is identified by the output.

16. The apparatus of claim 1 , wherein the output is an M-bit output, and the output generating logic is configured to select between bits belonging to different intermediary binary strings to generate an M-bit binary output that identifies M addresses in the identified subset when the number of addresses in said subset is greater than or equal to M.

17. The apparatus of claim 6 , wherein each combination logic unit is configured to sort its received predetermined selection of bits into an intermediary binary string containing fewer bits than the number of the predetermined selection of bits received by that combination logic unit.

18. The apparatus of claim 6 , wherein each combination logic unit comprises:
a plurality of sort units each configured to:
receive a portion of the received bits; and
sort the received portion of bits to group together the bits identifying addresses belonging to the identified subset to generate a preliminary binary string; and

one or more merge units, each of the one or more merge units being configured to receive a plurality of preliminary binary strings and to merge those preliminary binary strings to group together the bits from each received preliminary binary string that identify addresses belonging to the identified subset.

19. A method of identifying a set of M output memory addresses from a larger set of N input memory addresses, comprising:
performing a comparison of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset;
generating an output flag whose status indicates whether all addresses in the subset identified by the binary classification dataset have been output by output generating logic; and
generating an output containing an address in the identified subset of addresses.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses, the apparatus comprising:
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresse

Assignees

• Imagination Tech Ltd

Inventors

• Iuliano Luca
• Nield Simon
• Rose Thomas

Classifications

• G06F13/1631 Primary

  through address comparison · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F2212/1024

  Latency reduction · CPC title