Data selection for a processor pipeline using multiple supply lines

Patent metadata

Field	Value
Publication number	US-11429389-B2
Application number	US-202017104940-A
Country	US
Kind code	B2
Filing date	Nov 25, 2020
Priority date	Jan 16, 2017
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing pipelines, wherein each pipeline of the plurality of processing pipelines comprises:
a processing element having a first input and a second input, and
a first supply line and a second supply line;

wherein a first pipeline of the plurality of processing pipelines further comprises:
a first multiplexer operable to select a supply line so that data from a selected supply line is received at the first input of the first pipeline via the first multiplexer, and
a second multiplexer operable to select a supply line so that data from a selected supply line is received at the second input of the first pipeline via the second multiplexer;

wherein, in a first mode of operation and for the first pipeline:
the first multiplexer of the first pipeline is configured to select a supply line of another one of the plurality of pipelines,
the second multiplexer of the first pipeline is configured to select the second supply line of the first pipeline, and
the same data is provided on both the first and second supply lines of the first pipeline.

2. The processor as set forth in claim 1 , wherein in a second mode of operation and for the first pipeline, the first and second multiplexers of the first pipeline are configured to respectively select first and second supply lines of the first pipeline such that the processing element of the first pipeline receives data via the first and second supply lines of the first pipeline, wherein the first supply line of the first pipeline is capable of supplying data that is different to the data supplied by the second supply line of the first pipeline; and
the processor further comprising a controller configured to select the first mode or the second mode of operation for the processor in dependence on at least one instruction received for processing data at the processor.

3. The processor as set forth in claim 2 , wherein the controller is configured to select the first mode in response to the at least one instruction comprising an instruction for at least one of the processing elements to process data from private memory for another one of the processing elements.

4. The processor as set forth in claim 2 , wherein, in the first mode and for the first pipeline, the controller is configured to cause the second supply line to supply data from the same memory register as the first supply line.

5. The processor as set forth in claim 2 , wherein the controller is configured to select the first mode when the at least one instruction received for processing data at the processor is a gradient operation.

6. The processor as set forth in claim 5 , wherein the gradient operation is for determining the gradient between at least two pixel positions.

7. The processor as set forth in claim 2 , wherein the controller is configured to select the first mode when the at least one instruction received for processing data at the processor is a maximum operation.

8. The processor as set forth in claim 2 , wherein the controller is configured to select the first mode when the at least one instruction received for processing data at the processor is an averaging operation.

9. The processor as set forth in claim 8 , wherein the averaging operation is for determining an average value of at least two pixel positions.

10. The processor as set forth in claim 1 , wherein, for each pipeline, the first and second supply lines are configured to supply data from private memory for the processing element of that pipeline.

11. The processor as set forth in claim 1 , wherein, in the first mode and for the first pipeline, the first multiplexer selects one of the supply lines of another one of the plurality of pipelines so as to receive data from private memory for the processing element of the another pipeline.

12. The processor as set forth in claim 1 , wherein, the processor comprises more than two processing pipelines and, in the first mode, each of the first and second multiplexers of one of the processing pipelines is capable of selecting a supply line of the other processing pipelines.

13. The processor as set forth in claim 1 , wherein each processing element is a fused multiply-add arithmetic logic unit.

14. The processor as set forth in claim 1 , wherein the processor comprises four processing pipelines and each of the first and second multiplexers have no more than four selectable inputs.

15. The processor as set forth in claim 1 , wherein the processor is capable of concurrently supporting a plurality of threads.

16. A method of processing data at a processor comprising a plurality of pipelines, each pipeline of the plurality of pipelines comprising a processing element having a first input and a second input and a first supply line and a second supply line, wherein a first pipeline of the plurality of processing pipelines further comprises a first multiplexer operable to select a supply line so that data from a selected supply line is received at the first input of the first pipeline via the first multiplexer of the first pipeline and a second multiplexer operable to select a supply line so that data from a selected supply line is received at the second input of the first pipeline via the second multiplexer of the first pipeline, the method comprising:
in a first mode of operation and for the first pipeline:
selecting, by the first multiplexer of the first pipeline, a supply line of another one of the plurality of pipelines;
selecting, by the second multiplexer of the first pipeline, the second supply line of the first pipeline; and
supplying the same data on both the first and the second supply line of the first pipeline.

17. The method as set forth in claim 16 , the method comprising:
receiving at least one instruction for processing data;
selecting the first mode or a second mode of operation for the processor in dependence on the at least one instruction;
if the second mode is selected and for the first pipeline:
selecting, by the first and second multiplexers of the first pipeline respectively, the first and second supply lines of the first pipeline such that the processing element of the first pipeline receives data via the first and second supply lines of the first pipeline, wherein the first supply line of the first pipeline is capable of supplying data that is different to the data supplied by the second supply line of the first pipeline.

18. The method as set forth in claim 17 , wherein the first mode is selected in response to the at least one instruction comprising an instruction for at least one of the processing element to process data from private memory for another one of the processing elements.

19. The method as set forth in claim 16 , wherein, for each pipeline, the step of supplying the same data comprises supplying data from private memory for the processing element of that pipeline.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processor embodied in hardware on an integrated circuit, the processor comprising:
a plurality of processing pipelines, wherein each pipeline of said plurality of pipelines comprises:
a processing element having a first input and a second input, and
a first supply line and a second supply line;

wherein a first pipeline of the plurality of processing pipeli

Assignees

• Imagination Tech Ltd

Inventors

• Nield Simon
• Rose Thomas

Classifications

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/30189 Primary

  according to execution mode, e.g. mode flag · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title