Solder grid array for attachment of a die package

Patent metadata

Field	Value
Publication number	US-12557683-B2
Application number	US-202117556444-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Dec 20, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A die package comprises a substrate comprising a solder pad element, a semiconductor die coupled to the substrate, a solder layer comprising a first solder material deposited on the solder pad element, the first solder material having a first melting temperature, and an interconnect ball comprising a second solder material deposited on the solder layer, the second solder material having a second melting temperature that is less than the first melting temperature.

First claim

The invention claimed is:

1 . A die package comprising:
a substrate comprising a solder pad element; a semiconductor die coupled to the substrate; a solder layer comprising a first solder material on the solder pad element, the first solder material comprising tin (Sn), silver (Ag) and copper (Cu); and an interconnect ball comprising a second solder material in contact with the first solder material, wherein the second solder material comprises more bismuth (Bi) or indium (In) than the first solder material, and less Sn than the first solder material.

2 . The die package of claim 1 , wherein the first solder material has a melting temperature of at least 200° C.

3 . The die package of claim 2 , wherein the second solder material has a melting temperature of less than 200° C.

4 . The die package of claim 1 , wherein the solder layer has a thickness of less than 60 micrometers.

5 . The die package of claim 1 , wherein the substrate further comprises a solder resist opening, wherein the solder pad element is located within the solder resist opening and wherein the solder layer is located at least partially within the solder resist opening.

6 . The die package of claim 1 , wherein the first solder material comprises up to 5 wt. % silver (Ag), from 0.1 wt. % to 1 wt. % copper (Cu), and the balance tin (Sn).

7 . The die package of claim 1 , wherein the second solder material comprises at least 30 wt. % Bi or at least 20 wt. % In, and wherein the first solder material has less than 5 wt. % Bi.

8 . The die package of claim 7 , wherein the first solder material comprises at least 90 wt. % Sn, and wherein the second solder material comprises less than 80 wt. % Sn.

9 . The die package of claim 1 , wherein the semiconductor die is one of a memory device, a computer processing unit (CPU), a graphics processing unit (GPU), or a processor.

10 . An electronic device comprising:
a circuit board; and a die package coupled to the circuit board with one or more interconnect structures, wherein the die package comprises a substrate comprising a solder pad element and a semiconductor die coupled to the substrate, and wherein each of the one or more interconnect structures comprises:
a solder layer comprising a first solder material of primarily Sn on the solder pad element, the first solder material having a first melting temperature; and
an interconnect ball comprising a second solder material deposited on the solder layer and electrically connected to the circuit board, the second solder material having a second melting temperature that is less than the first melting temperature and comprising more bismuth (Bi) or indium (In) than the first solder material, and less Sn than the first solder material.

11 . The electronic device of claim 10 , wherein the solder layer has a thickness of less than 60 micrometers.

12 . The electronic device of claim 10 , wherein the substrate further comprises a solder resist opening, wherein the solder pad element is formed in the solder resist opening.

13 . The electronic device of claim 10 , wherein the first solder material comprises up to 5 wt. % silver (Ag), from 0.1 wt. % to 1 wt. % copper (Cu), and the balance tin (Sn).

14 . The electronic device of claim 10 , wherein the second solder material comprises at least 30 wt. % Bi or at least 20 wt. % In, and wherein the first solder material has less than 5 wt. % Bi.

15 . The electronic device of claim 14 , wherein the first solder material comprises at least 90 wt. % Sn, and wherein the second solder material comprises less than 80 wt. % Sn.

16 . A method of manufacturing a die package, the method comprising:
depositing a first solder material onto a solder pad element of a die package substrate so that the first solder material forms a solder layer on the solder pad element, wherein the first solder material has a first melting temperature; landing an electrical testing probe on the first solder material; and depositing a second solder material onto the solder layer so that the second solder material forms an interconnect ball on the solder layer, wherein the second solder material has a second melting temperature that is less than the first melting temperature.

17 . The method of claim 16 , further comprising electronically testing a semiconductor die electrically coupled to the die package substrate via the probe in contact with the solder layer before depositing the second solder material onto the solder layer.

18 . The method of claim 16 , wherein depositing the first solder material comprises depositing a first solder paste or flux onto the solder pad element and reflowing the first solder paste or flux to form a tin (Sn), silver (Ag) and copper (Cu) alloy as the solder layer.

19 . The method of claim 18 , wherein depositing the first solder paste or flux comprises printing the first solder paste onto the solder pad element.

20 . The method of claim 19 , wherein printing the first solder paste or flux comprises at least one of pin dipping the first solder paste or flux or stencil printing the first solder paste or flux.

21 . The method of claim 18 , wherein depositing the first solder material further comprises depositing a first solder ball on the first solder paste or flux, wherein the reflowing comprises reflowing the first solder paste or flux and the first solder ball to form the solder layer.

22 . The method of claim 16 , wherein depositing the second solder material comprises depositing a second solder paste or flux onto the solder layer and reflowing the second solder paste or flux at a temperature that is lower than a melting temperature of the first solder material to form the interconnect ball from an alloy comprising more bismuth (Bi) or indium (In) than the first solder material, and less Sn than the first solder material.

23 . The method of claim 22 , wherein depositing the second solder material further comprises depositing a second solder ball on the second solder paste or flux, wherein the reflowing comprises reflowing the second solder paste or flux and the second solder ball to form the interconnect ball.

24 . The method of claim 16 , wherein depositing the first solder material onto the solder pad element includes depositing the first solder material into a solder resist opening in the die package substrate.

Assignees

• Intel Corp

Inventors

• Ayalasomayajula Mukund
• Padmanabhan Ramalekshmi Thanu Dinesh
• Zhang Rui
• Lu Xiao
• Nickerson Robert
• Stover Patrick Neel

Classifications

• H10W72/072 Primary

  of bump connectors · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/90

  Bond pads, in general · CPC title