Substrate architecture for solder joint reliabilty in microelectronic package structures and methods of forming the same

Patent metadata

Field	Value
Publication number	US-2019104610-A1
Application number	US-201715720488-A
Country	US
Kind code	A1
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Apr 4, 2019
Grant date	—

Abstract

Methods/structures of joining package structures are described. Those methods/structures may include a first substrate comprising a first die, wherein an underfill material is disposed on a first surface of the first substrate adjacent the first die; and a second substrate disposed on the first substrate, wherein the second substrate comprises at least one opening disposed over the first die, wherein the at least one opening is at least partially filled with the underfill material.

First claim

1 . A microelectronic package structure comprising:
a first substrate; a first die on a surface of the first substrate; an underfill material on the surface of the first substrate adjacent the first die; a second substrate over the first die, wherein the second substrate comprises at least one opening, wherein the at least one opening is within a footprint of the first die, and wherein the at least one opening is at least partially filled with the underfill material; and a second die on the second substrate and over the at least one opening.

2 . The microelectronic package structure of claim 1 , wherein a width of the at least one opening comprises between about 30 microns to about 1000 microns.

3 . The microelectronic package structure of claim 1 wherein the at least one opening is within the footprint of the second die.

4 . The microelectronic package structure of claim 1 wherein the second substrate comprises an interposer, and wherein the underfill substantially fills the at least one opening.

5 . The microelectronic package structure of claim 1 wherein the second die is on a first side of the second substrate, and wherein a gap is between a top surface of the first die and a second side of the second substrate, wherein the second side is opposite the first side.

6 . The microelectronic package structure of claim 1 wherein a portion of the underfill comprises a surface, wherein the surface is coplanar with a top surface of the first die.

7 . The microelectronic package structure of claim 1 wherein the die comprises a system on a chip die.

8 . The microelectronic package structure of claim 1 wherein the microelectronic package structure comprises a package on package assembly.

9 . A method of forming a microelectronic package structure comprising:
forming at least one opening in a central portion of an upper substrate; attaching the upper substrate to a lower substrate, wherein the lower substrate comprises a first die on a surface of the lower substrate; dispensing an underfill material within the at least one opening, wherein the at least one opening is at least partially filled with the underfill material; forming the underfill material adjacent the first die; attaching a second die on the upper substrate, wherein the at least one opening is within a footprint of the second die.

10 . The method of forming the microelectronic package structure of claim 9 wherein attaching the upper substrate further comprises placing the at least opening within a footprint of the first die.

11 . The method of forming the microelectronic package structure of claim 9 further comprising forming the underfill material adjacent solder joints between the upper substrate and the lower substrate.

12 . The method of forming the microelectronic package structure of claim 9 wherein forming the at least one opening comprises laser drilling the at least one opening.

13 . The method of forming the microelectronic package structure of claim 9 wherein the lower substrate comprises a plurality of die on a first side of the lower substrate.

14 . The method of forming the microelectronic package structure of claim 13 further comprising dispensing the underfill material in a gap between the upper substrate and the lower substrate.

15 . The method of forming the microelectronic package structure of claim 14 wherein the gap comprises a width of between about 130 microns and about 180 microns.

16 . The method of forming the microelectronic package structure of claim 9 , wherein the microelectronic package structure comprises a package on package assembly.

17 . A microelectronic system, comprising:
a board; a microelectronic package assembly attached to the board, wherein the microelectronic package comprises:
a first substrate;
a die on the first substrate, wherein an underfill material is on a first surface of the first substrate adjacent the die; and
a second substrate over the first die, wherein the second substrate comprises at least one opening over the die, and wherein the at least one opening is at least partially filled with the underfill material, and wherein the at least one opening is within a footprint of the first die.

18 . The microelectronic system of claim 17 , wherein the die comprises a first die, and further comprising a second die on the second substrate, wherein the at least one opening is within a footprint of the second die.

19 . The microelectronic system of claim 17 wherein the at least one opening comprises a width of between about 100 microns to about 1000 microns.

20 . The microelectronic system of claim 17 wherein a depth of the at least one opening is equal to a height of the second substrate.

21 . The microelectronic system of claim 17 wherein at least one solder structure is between the first substrate and the second substrate in a peripheral portion of the first substrate, and wherein a portion of the underfill material is adjacent the at least one solder structure, and wherein a surface of the portion of the underfill material is coplanar with a top surface of the first die.

22 . The microelectronic system of claim 21 wherein a height of the solder structure is above the surface of the portion of the underfill material.

23 . The microelectronic system of claim 17 wherein the at least one opening is substantially filled with the underfill material.

24 . The microelectronic package system of claim 17 wherein the die comprises a system on a chip.

25 . The microelectronic system of claim 17 wherein the microelectronic package assembly comprises a package on package assembly.

Assignees

• Intel Corp

Inventors

• Nickerson Robert
• Deshpande Nitin
• Karhade Omkar
• De Bonis Thomas

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W74/10 Primary

  characterised by their shape or disposition · CPC title

• H05K1/0256 Primary

  Electrical insulation details, e.g. around high voltage areas · CPC title

• H05K3/0044

  Mechanical working of the substrate, e.g. drilling or punching (H05K3/0008 takes precedence) · CPC title