Minimizing redundancy for stuck bit coding
US-12450119-B2 · Oct 21, 2025 · US
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Mateescu Robert patents
Mateescu Robert is listed as an inventor on 33 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mateescu Robert |
| Total patents | 33 |
| First publication | Jun 25, 2015 |
| Latest publication | Oct 21, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Three dimensional nand multiply and accumulate with dynamic inputs
US-2025238202-A1 · Jul 24, 2025 · US
Stuck bits encoding and decoding on a storage device
US-12362029-B2 · Jul 15, 2025 · US
Minimizing redundancy for stuck bit coding
US-2025190302-A1 · Jun 12, 2025 · US
Stuck bits encoding and decoding on a storage device
US-2025157562-A1 · May 15, 2025 · US
Privacy-preserving distributed computing
US-2024146700-A1 · May 2, 2024 · US
Computational resource allocation in ensemble machine learning systems
US-11487580-B2 · Nov 1, 2022 · US
Computational resource allocation in ensemble machine learning systems
US-2021073036-A1 · Mar 11, 2021 · US
Wear leveling in non-volatile storage
US-10228878-B1 · Mar 12, 2019 · US
Bad page and bad block management in memory
US-10223018-B2 · Mar 5, 2019 · US
Recent patents
Latest publications not already listed above.
Cache oblivious algorithm for butterfly code
US-10164655-B2 · Dec 25, 2018 · US
Storage cluster and method that efficiently store small objects with erasure codes
US-10120576-B2 · Nov 6, 2018 · US
Bad Page And Bad Block Management In Memory
US-2018307431-A1 · Oct 25, 2018 · US
Error correction for non-volatile memory
US-9959166-B2 · May 1, 2018 · US
Repair-Optimal Parity Code
US-2018034475-A1 · Feb 1, 2018 · US
Encoding scheme for 3D vertical flash memory
US-9830219-B2 · Nov 28, 2017 · US
Repair-optimal parity code
US-9793922-B2 · Oct 17, 2017 · US
Doorless protocol having multiple queue read requests in flight
US-9778859-B2 · Oct 3, 2017 · US
Storage cluster and method that efficiently store small objects with erasure codes
US-2017262187-A1 · Sep 14, 2017 · US
Inter-cell interference reduction in flash memory devices
US-9704594-B1 · Jul 11, 2017 · US
Error correction for non-volatile memory
US-2017192846-A1 · Jul 6, 2017 · US
Systems and methods for sending data from non-volatile solid state devices before error correction
US-2017141878-A1 · May 18, 2017 · US
Doorbell-less protocol for solid state drive interface
US-9652199-B2 · May 16, 2017 · US
Error correction for non-volatile memory
US-9619320-B2 · Apr 11, 2017 · US
Repair-Optimal Parity Code
US-2017093425-A1 · Mar 30, 2017 · US
Cache Oblivious Algorithm for Butterfly Code
US-2017093426-A1 · Mar 30, 2017 · US
ACK-less protocol for noticing completion of read requests
US-9547472-B2 · Jan 17, 2017 · US
Acknowledgement-less protocol for solid state drive interface
US-9535870-B2 · Jan 3, 2017 · US
Doorbell-less endpoint-initiated protocol for storage devices
US-9513869-B2 · Dec 6, 2016 · US
Error correction for non-volatile memory
US-2016246670-A1 · Aug 25, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Western Digital Tech Inc | 20 |
| HGST Netherlands BV | 14 |
| Sandisk Technologies Llc | 2 |
| Western Digital Technolgies Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0659 | 10 |
| H03M13/13 | 9 |
| G06F11/1012 | 9 |
| G06F11/1068 | 8 |
| G06F3/0679 | 7 |