Encoding scheme for 3D vertical flash memory

Patent metadata

Field	Value
Publication number	US-9830219-B2
Application number	US-201514627580-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Sep 15, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.

First claim

What is claimed is:

1. A method of encoding data for writing to a memory comprising:
writing first data to a plurality of memory cells in the memory of a 3d arrangement;
reading the first data from the plurality of memory cells in the memory;
analyzing the first read data to determine whether the first read data includes an error indicative of a defect in one of the plurality of memory cells;
when one of the plurality of memory cells is defective, encoding distinct second data based on a location of the defective one of the plurality of memory cells; and
writing the encoded second data to the memory, wherein writing the encoded second data to the memory comprises writing at least a part of the encoded second data to a memory cell that is immediately next to the defective one of the plurality of memory cells to intentionally cause inter-cell interference to the defective one of the plurality of memory cells to increase a threshold voltage in the interfering cell, wherein the three-dimensional flash memory comprises a plurality of word lines having multi-level cells, wherein the encoded second data is written to one of an upper page of a first adjacent word line different from a word line containing the first data and a lower page of a second adjacent word line different from the word line containing the first data.

2. The method of claim 1 , wherein the memory is a non-volatile memory storage system.

3. The method of claim 2 , wherein the non-volatile memory storage system is a solid state drive.

4. The method of claim 3 , wherein the solid state drive is three-dimensional flash memory.

5. The method of claim 1 , wherein the reading comprises reading the first data from the memory based on a predetermined threshold.

6. The method of claim 5 , wherein the predetermined threshold is a read voltage level threshold.

7. The method of claim 6 , wherein the analyzing comprises comparing the first data read from the memory to a copy of the first data different from the first data stored in the memory.

8. The method of claim 1 , wherein the adjacent memory cell is in a different word line compared to the defective one of the plurality of memory cells.

9. The method of claim 1 , wherein the reading comprises reading the first data from the memory based on a plurality of predetermined thresholds.

10. The method of claim 9 , wherein the analyzing comprises comparing the first data read from the memory based on a first of the plurality of predetermined thresholds and the first data read from the memory based on a second of the plurality of predetermined thresholds that is different from the first predetermined threshold.

11. The method of claim 1 , wherein the encoding is performed by a flash memory controller.

12. The method of claim 1 , wherein the error is caused by detrapping.

13. The method of claim 1 , wherein the second data is written to memory at the position to cause inter-cell interference with the first data.

14. A non-transitory computer program product comprised of a series of instructions executable on a computer, the series of instructions operable to perform a process for encoding data for writing to a memory; the series of instructions implementing the steps of:
writing first data to a plurality of memory cells in the memory of a 3d arrangement;
reading the first data from the plurality of memory cells in the memory;
analyzing the read first data to determine whether the first read data includes an error indicative of a defect in one of the plurality of memory cells;
when one of the plurality of memory cells is defective, encoding distinct second data based on a location of the defective one of the plurality of memory cells; and
writing the encoded second data to the memory, wherein writing the encoded second data to the memory comprises writing at least a part of the encoded second data to a memory cell that is immediately next to the defective one of the plurality of memory cells to intentionally cause inter-cell interference to the defective one of the plurality of memory cells to increase a threshold voltage in the interfering cell, wherein the three-dimensional flash memory comprises a plurality of word lines having multi-level cells, wherein the encoded second data is written to one of an upper page of a first adjacent word line different from a word line containing the first data and a lower page of a second adjacent word line different from the word line containing the first data.

15. A system for encoding data for writing to a memory, the system comprising:
a writing module configured to write first data to a plurality of memory cells in the memory of a 3d arrangement;
a reading module configured to read the first data from the plurality of memory cells in the memory;
an analyzing module configured to analyze the first read data to determine whether the first read data includes an error indicative of a defect in one of the plurality of memory cells;
an encoding module configured to encode distinct second data based on a location of the defective one of the plurality of memory cells; and
an encoded data writing module configured to write the encoded second data to the memory, wherein writing the encoded second data to the memory comprises writing at least a part of the encoded second data to a memory cell that is immediately next to the defective one of the plurality of memory cells to intentionally cause inter-cell interference to the defective one of the plurality of memory cells to increase a threshold voltage in the interfering cell, wherein the three-dimensional flash memory comprises a plurality of word lines having multi-level cells, wherein the encoded second data is written to one of an upper page of a first adjacent word line different from a word line containing the first data and a lower page of a second adjacent word line different from the word line containing the first data.

16. The system of claim 15 , wherein the encoding module comprises a flash memory controller.

Assignees

• Western Digital Tech Inc

Inventors

• Mateescu Robert
• Kim Yongjune
• Bandic Zvonimir Z
• Song Seung-Hwan

Classifications

• G11C2029/0409

  Online test · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title