Error correction for non-volatile memory

Patent metadata

Field	Value
Publication number	US-9619320-B2
Application number	US-201514627570-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Feb 20, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

First claim

What is claimed is:

1. A method, implemented by a processor, of error correcting data for writing to a memory, the method comprising:
determining whether the memory includes a defective memory cell;
receiving a message to be written to the memory;
sub-dividing the message into a plurality of sub-messages;
generating a first error correction code for the sub-messages, the first error correction code being a first type;
generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, wherein a size of each of the plurality of sub-messages corresponds to a number of bits necessary for a second error correction code of the plurality of second error correction codes to mask the defective memory cell;
generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes; and
writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

2. The method of claim 1 , wherein the memory is a non-volatile memory storage system, memory module, or CPU cache memory.

3. The method of claim 2 , wherein the non-volatile memory storage system is a solid state drive.

4. The method of claim 1 , wherein an output of the defective memory cell is the same for different inputs to the defective memory cell.

5. The method of claim 1 , wherein each of the sub-divided messages is of an equal amount of data.

6. The method of claim 5 , wherein the sub-dividing of the message is based on the plurality of second error correction codes.

7. The method of claim 1 , wherein the first error correction code is an error correction code for random errors.

8. The method of claim 7 , wherein the random errors are due to noise in the memory.

9. The method of claim 1 , wherein each of the plurality of second error correction codes corresponds to a single sub-message.

10. The method of claim 9 , wherein one of the plurality of second error correction codes is an error correction code for masking the defective memory cell.

11. The method of claim 9 , wherein each of the plurality of second error correction codes are a single bit.

12. The method of claim 11 , wherein a value of one of the plurality of second error correction codes is based on a value of the defective memory cell.

13. The method of claim 12 , further comprising:
determining whether the value of the defective memory cell matches a value of the sub-message.

14. The method of claim 13 , further comprising:
determining whether the value of the of the defective memory cell matches an opposite of the value of the sub-message.

15. The method of claim 14 , wherein the value of the one of the plurality of second error correction codes is set to one or zero based on the determination of whether the value of the defective memory cell matches the value of the sub-message, and whether the value of the of the defective memory cell matches the opposite of the value of the sub-message.

16. The method of claim 1 , wherein determining whether the memory includes the defective memory cell comprises reading previously written data from the memory.

17. The method of claim 16 , wherein the determining further comprises comparing the read data to a predetermined data pattern.

18. The method of claim 1 , further comprising:
generating a second combined message for a second message to be written to the memory based on the determination of whether the memory includes the defective memory cell; and
writing the second combined message to the memory.

19. A computer program product comprised of a series of instructions executable on a computer, the computer program product performing a process for encoding data for writing to a memory; the computer program implementing the steps of:
determining whether the memory includes a defective memory cell;
receiving a message to be written to the memory;
sub-dividing the message into a plurality of sub-messages;
generating a first error correction code for the sub-messages, the first error correction code being a first type;
generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, wherein a size of each of the plurality of sub-messages corresponds to a number of bits necessary for a second error correction code of the plurality of second error correction codes to mask the defective memory cell;
generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes; and
writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

20. A system for encoding data for writing to a memory, the system comprising:
a determining module that determines whether the memory includes a defective memory cell;
a receiving module that receives a message to be written to the memory;
a sub-dividing module that sub-divides the message into a plurality of sub-messages;
a first error correction code generating module that generates a first error correction code for the sub-messages, the first error correction code being a first type;
a second error correction code generating module that generates a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, wherein a size of each of the plurality of sub-messages corresponds to a number of bits necessary for a second error correction code of the plurality of second error correction codes to mask the defective memory cell;
a combined message generating module that generates a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes; and
a writing module that writes the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Assignees

• HGST Netherlands BV
• Western Digital Tech Inc

Inventors

• Mateescu Robert
• Bandic Zvonimir Z
• Kim Yongjune
• Song Seung-Hwan

Classifications

• H03M13/1105

  Decoding · CPC title

• G06F11/1008 Primary

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• H03M13/611

  Specific encoding aspects, e.g. encoding by means of decoding · CPC title

• H03M13/13

  Linear codes · CPC title

• H03M13/356

  Unequal error protection [UEP] · CPC title