Computational resource allocation in ensemble machine learning systems

Patent metadata

Field	Value
Publication number	US-11487580-B2
Application number	US-201916563776-A
Country	US
Kind code	B2
Filing date	Sep 6, 2019
Priority date	Sep 6, 2019
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

First claim

What is claimed is:

1. A system comprising:
a processor to execute a plurality of classifiers, each classifier of the plurality of classifiers having a respective relative importance;
a memory array;
a memory controller to allocate memory from the memory array to each of the plurality of classifiers; and
an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon the respective relative importance of the at least one of the plurality of classifiers, wherein the memory controller allocates the memory from the memory array to the at least one of the plurality of classifiers based upon the determined optimized bit precision value.

2. The system of claim 1 , wherein the relative importance is determined based upon a weight assigned to each of the plurality of classifiers, wherein a first classifier of the plurality of classifiers having a first weight is more important than a second classifier of the plurality of classifiers having a second weight that is smaller than the first weight.

3. The system of claim 2 , wherein the optimized bit precision value of the first classifier of the plurality of classifiers is greater than the optimized bit precision value of the second classifier of the plurality of classifiers.

4. The system of claim 1 , wherein an amount of the memory allocated to a first classifier of the plurality of classifiers having a first optimized bit precision value is greater than the amount of the memory allocated to a second classifier of the plurality of classifiers having a second optimized bit precision value that is smaller than the first optimized bit precision value.

5. The system of claim 1 , wherein the optimization processor determines the relative importance of the plurality of classifiers before determining the optimized bit precision value.

6. The system of claim 1 , wherein the optimization processor determines an amount of the memory to be allocated to each of the plurality of classifiers based upon the optimized bit precision value.

7. The system of claim 6 , wherein the optimization processor comprises a look-up table comprising the amount of the memory corresponding to the optimized bit precision value, wherein the optimized bit precision value is input into the look-up table to obtain the amount of the memory as an output of the look-up table.

8. The system of claim 1 , wherein at least one of the plurality of classifiers is a decision tree.

9. The system of claim 1 , wherein at least one of the plurality of classifiers is a linear classifier.

10. The system of claim 1 , wherein at least one of the plurality of classifiers is a deep neural network.

11. The system of claim 1 , wherein the plurality of classifiers are implemented in an adaptive bosting algorithm.

12. The system of claim 1 , wherein the optimization processor determines the optimized bit precision value to minimize a mismatch probability between an output of an ideal memory allocation and the output of an actual memory allocation.

13. A method comprising:
determining, by an optimization processor associated with a memory controller, a respective relative importance of each classifier of a plurality of classifiers;
determining, by the optimization processor, an optimized bit precision value for at least one of the plurality of classifiers having high relative importance;
determining, by the optimization processor, an optimized amount of memory for the at least one of the plurality of classifiers based on the optimized bit precision value; and
allocating, by the memory controller, the optimized amount of memory from a memory array to the at least one of the plurality of classifiers.

14. The method of claim 13 , further comprising determining the relative importance of the plurality of classifiers based upon a weight assigned to each of the plurality of classifiers, wherein a first classifier of the plurality of classifiers that has a first weight is more important than a second classifier of the plurality of classifiers that has a second weight that is smaller than the first weight.

15. The method of claim 14 , wherein the optimized bit precision value of the first classifier is greater than the optimized bit precision value of the second classifier.

16. The method of claim 15 , wherein the optimized amount of memory for the first classifier is greater than the optimized amount of memory for the second classifier.

17. The method of claim 13 , wherein each of the plurality of classifiers is one of a decision tree, a single layer neural network, a support vector machine, or a deep neural network.

18. A non-transitory computer-readable media comprising computer-readable instructions stored thereon that when executed by an optimization processor cause the optimization processor to:
determine a first optimized bit precision value for a first classifier of an adaptive boosting algorithm based upon minimizing a first mismatch probability of the first classifier;
determine a second optimized bit precision value for a second classifier of the adaptive boosting algorithm based upon minimizing a second mismatch probability of the second classifier;
allocate a first amount of memory to the first classifier based on the first optimized bit precision value; and
allocate a second amount of memory to the second classifier based on the second optimized bit precision value,
wherein the first classifier has a first relative importance, the second classifier has a second relative importance and the first relative importance is greater than the second relative importance;
wherein the first optimized bit precision value is greater than the second optimized bit precision value; and
wherein the first amount of memory is greater than the second amount of computational resource.

19. The non-transitory computer-readable media of claim 18 , wherein.

20. The non-transitory computer-readable media of claim 18 , wherein a weight assigned to the first classifier is greater than the weight assigned to the second classifier.

21. A memory device comprising:
a memory array;
a memory controller to allocate memory from the memory array to each of a plurality of classifiers, each classifier of the plurality of classifiers having a respective relative importance that is determined based on a respective weight assigned to each of the plurality of classifiers; and
an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon the relative importance of the at least one of the plurality of classifiers, wherein the memory controller allocates the memory from the memory array to the at least one of the plurality of classifiers based upon the determined optimized bit precision value.

22. The memory device of claim 21 , wherein a first classifier of the plurality of classifiers having a first weight is more important than a second classifier of the plurality of classifiers having a second weight that is smaller than the first weight.

23. The memory device of claim 22 , wherein the optimized bit precision value of the first classifier of the plurality of classifiers is greater than the optimized bit precision value of the second classifier of the plurality of classifiers.

24. The memory device of claim 21 , wherein an amount of the memory allocated to a first classifier of the plurality of classifiers having a first optimized bit precision va

Assignees

• Western Digital Tech Inc

Inventors

• Kim Yongjune
• Cassuto Yuval
• Mateescu Robert
• Guyot Cyril

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F9/5016 Primary

  the resource being the memory · CPC title

• G06F18/24323

  Tree-organised classifiers · CPC title

• G06F18/24133

  Distances to prototypes · CPC title

• G06N5/01

  Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound · CPC title