Inter-cell interference reduction in flash memory devices

Patent metadata

Field	Value
Publication number	US-9704594-B1
Application number	US-201615047113-A
Country	US
Kind code	B1
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

The present disclosure relates to apparatus, systems, and methods that address the migration of least significant in memory cells due to inter-cell interference (ICI). The disclosed embodiments include a control unit that is configured to characterize the vulnerability of memory cells to ICI, and appropriately encode data stored in the vulnerable memory cells to address ICI. This encoding scheme, referred to as “stuck-at” encoding scheme, can be separate from the generic error correcting code encoding. The stuck-at encoding scheme can decrease the bit error rate of flash memory devices.

First claim

The invention claimed is:

1. A method comprising:
determining, by a control unit of a memory device comprising a first memory cell, a voltage level of the first memory cell in an erased state;
receiving, at the control unit from a host device, a first request to store a first data to the memory device comprising the first memory cell;
encoding, by the control unit, the first data to generate an encoded first data, wherein a logical value of the encoded first data corresponding to a least significant bit of the first memory cell is a predetermined logical value regardless of a content of the first data when the voltage level of the first memory cell is within a predetermined voltage range; and
storing, by the control unit, the logical value of the encoded first data to the least significant bit of the first memory cell,
wherein encoding the first data further comprises encoding the first data using a decodable function that provides the predetermined logical value for the least significant bit of the first memory cell when the voltage level of the first memory cell is greater than a predetermined threshold.

2. The method of claim 1 , wherein the predetermined threshold is determined, in part, based on a histogram of voltage levels of all memory cells in the memory device in their erased state.

3. The method of claim 1 , wherein the predetermined logical value for the least significant bit of the first memory cell is zero.

4. The method of claim 1 , wherein encoding the first data comprises encoding the first data using error correcting code.

5. The method of claim 1 , further comprising receiving, at the control unit, a second request to store a second data to the memory device comprising a second memory cell, wherein the second memory cell is capacitively coupled to the first memory cell, wherein encoding the first data to generate the encoded first data comprises encoding the first data in part based on a logical value of the second data to be written into a least significant bit of the second memory cell.

6. The method of claim 5 , wherein the first data is associated with a first page and the second data is associated with a second page.

7. The method of claim 1 , wherein the memory cell is a two-bit multi-level cell.

8. A storage system comprising:
a memory device comprising a first memory cell for maintaining data; and
a control unit configured to:
determine voltage level of the first memory cell in an erased state;
receive, from a host device in communication with the storage system, a first request to store a first data to the memory device comprising the first memory cell;
encode the first data to generate an encoded first data, wherein a logical value of the encoded first data corresponding to a least significant bit of the first memory cell is a predetermined logical value regardless of a content of the first data when the voltage level of the first memory cell is within a predetermined voltage range; and
store the logical value of the encoded first data to the least significant bit of the first memory cell,
wherein the control unit is configured to encode the first data using a decodable function that provides the predetermined logical value for the least significant bit of the first memory cell when the voltage level of the first memory cell is greater than a predetermined threshold.

9. The system of claim 8 , wherein the predetermined threshold is determined, in part, based on a histogram of voltage levels of all memory cells in the memory device in their erased state.

10. The system of claim 8 , wherein the predetermined logical value for the least significant bit of the first memory cell is zero.

11. The system of claim 8 , wherein the control unit is further configured to receive a second request to store a second data to the memory device comprising a second memory cell, wherein the second memory cell is capacitively coupled to the first memory cell, and encode the first data in part based on a logical value of the second data to be written into a least significant bit of the second memory cell.

12. The system of claim 11 , wherein the first data is associated with a first page and the second data is associated with a second page.

13. The system of claim 8 , wherein the memory cell is a two-bit multi-level cell.

14. A non-transitory computer readable medium having executable instructions operable to cause a control unit to:
determine a voltage level of a first memory cell in a memory device at an erased state;
receive, from a host device, a first request to store a first data to the memory device comprising the first memory cell;
encode the first data to generate an encoded first data, wherein a logical value of the encoded first data corresponding to a least significant bit of the first memory cell is a predetermined logical value regardless of a content of the first data when the voltage level of the first memory cell is within a predetermined voltage range; and
store the logical value of the encoded first data to the least significant bit of the first memory cell,
wherein the computer readable medium comprises executable instructions operable to cause the control unit to encode the first data using a decodable function that provides the predetermined logical value for the least significant bit of the first memory cell when the voltage level of the first memory cell is greater than a predetermined threshold.

15. The computer readable medium of claim 14 , wherein the predetermined threshold is determined, in part, based on a histogram of voltage levels of all memory cells in the memory device in their erased state.

16. The computer readable medium of claim 14 , further comprising executable instructions operable to cause the control unit to:
receive a second request to store a second data to the memory device comprising a second memory cell, wherein the second memory cell is capacitively coupled to the first memory cell, and
encode the first data in part based on a logical value of the second data to be written into a least significant bit of the second memory cell.

17. The computer readable medium of claim 14 , wherein the memory cell is a two-bit multi-level cell.

Assignees

• Western Digital Tech Inc
• Western Digital Technolgies Inc

Inventors

• Qin Minghai
• Mateescu Robert
• Song Seung-Hwan
• Bandic Zvonimir Z

Classifications

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title