Read-with-invalidate modified data in a cache line in a cache memory

Patent metadata

Field	Value
Publication number	US-10831658-B2
Application number	US-201916239455-A
Country	US
Kind code	B2
Filing date	Jan 3, 2019
Priority date	Jan 3, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

First claim

What is claimed:

1. An apparatus coupled to a first memory and a second memory, comprising:
a memory controller to cache data in the first memory that is stored in the second memory and to:
receive at least one read-with-invalidate command to read and invalidate one portion of a plurality of portions of a cache line having modified data;
indicate as invalid a portion indicator in an entry for the cache line in a table for the portion indicated in the read-with-invalidate command as invalid, wherein the table includes an entry for each of cache lines in the first memory, wherein each entry in the table includes portion indicators for portions of data in the cache line; and
invalidate the cache line in response to receipt of at least one read-with-invalidate command for at least one portion of the cache line.

2. The apparatus of claim 1 , wherein the cache line is invalidated in response to receipt of read-with-invalidate commands for all portions of the cache line and not invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

3. The apparatus of claim 1 , wherein the memory controller is further to:
allocate a cache line in response to a new data request, wherein pre-existing data in the allocated cache line that was invalidated is not copied to the second memory, and wherein cache lines having portions partially invalidated have a lower eviction priority and are allocated for new data after cache lines that have modified data and do not have any portion invalidated.

4. The apparatus of claim 1 , wherein the memory controller is further to:
determine that there is no cache line in the first memory for a target address of a read-with-invalidate command; and
access data from the second memory to return to the read-with-invalidate command, wherein the accessed data is not stored in an allocated cache line in the first memory.

5. The apparatus of claim 1 , wherein the memory controller is further to:
select the cache line to allocate for data for a target address to add to the first memory, wherein the cache line is not copied to the second memory in response to having received read-with-invalidate commands to read and invalidate all portions of the cache line; and
copy the selected cache line to the second memory in response to determining that read-with-invalidate commands were not received for all of the portions of the cache line.

6. The apparatus of claim 1 , wherein the cache line comprises a first cache line, wherein the memory controller is further to:
select the first cache line to allocate for new data to add to the first memory, wherein the first cache line is replaced without copying to the second memory in response to receipt of read-with-invalidate commands to read and invalidate all portions of the cache line; and
select a second cache line to allocate for new data to add to the first memory in response to determining that read-with-invalidate commands were received for less than all portions of the first cache line.

7. The apparatus of claim 1 , wherein there is one portion indicator for each portion of the portions of the cache line, wherein the cache line is replaced without copying to the second memory in response to at least one portion indicator for the cache line indicating the at least one portion of the cache line has invalid data.

8. The apparatus of claim 7 , wherein the memory controller is further to:
maintain a tag table including an entry for each cache line in the first memory indicating an address of the data in the cache line in the first memory, a valid flag indicating whether the cache line has valid data and a dirty flag indicating whether the cache line has modified data; and
set the valid flag and the dirty flag in an entry in tag table for the cache line to indicate invalid data and unmodified data, respectively, in response to all the portion indicators in an entry in the table for the cache line indicating invalid data.

9. The apparatus of claim 7 , wherein the memory controller is further to:
maintain a tag table including an entry for each cache line in the first memory indicating an address of the data in the cache line in the first memory, a dirty flag indicating whether the cache line has modified data, and the portion indicators for each portion of data of the portions of data of the cache line.

10. The apparatus of claim 1 , wherein the first memory comprises a volatile memory device and the second memory comprises a byte addressable non-volatile memory to cache data stored in the second memory.

11. A system, comprising:
at least one processing unit;
a memory controller;
a first memory coupled to the memory controller; and
a second memory coupled to the memory controller, wherein data evicted from the first memory is stored in the second memory;
wherein the memory controller manages data in the first memory and the second memory to:
receive at least one read-with-invalidate command to read and invalidate one portion of a plurality of portions of a cache line having modified data;
indicate as invalid a portion indicator in an entry for the cache line in a table for the portion indicated in the read-with-invalidate command as invalid, wherein the table includes an entry for each of cache lines in the first memory, wherein each entry in the table includes portion indicators for portions of data in the cache line; and
invalidate the cache line in response to receipt of at least one read-with-invalidate command for at least one portion of the cache line.

12. The system of claim 11 , further comprising:
boot service firmware to:
initialize the system including the at least one processing unit, the first memory, and the second memory;
determine whether read-with-invalidate commands are supported; and
configure memory controller to enable processing of read-with-invalidate commands to invalidate portions of a cache line in the first memory; and

processor firmware to:
initialize the at least one processing unit;

determine whether read-with-invalidate commands are supported; and
configure the at least one processing unit to enable use of read-with-invalidate commands to invalidate portions of a cache line in the first memory that are accessed a last time.

13. The system of claim 11 , wherein the cache line is invalidated in response to receipt of read-with-invalidate commands for all the portions of the cache line and not invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

14. The system of claim 11 , wherein the memory controller is further to:
determine that there is no cache line in the first memory for a target address of a read-with-invalidate command; and
access data from the second memory to return to the read-with-invalidate command, wherein the accessed data is not stored in an allocated cache line in the first memory.

15. The system of claim 11 , wherein the cache line comprises a first cache line, wherein the memory controller is further to:
select the first cache line to allocate for new data to add to the first memory, wherein the first cache line is replaced without copying to the second memory in response to receipt of read-with-invalidate commands to read and invalidate all portions of the cache line; and
select a second cache line to allocate for new data to add to the first memory in response to determining that read-with-invalidate commands were received for less than all portions of the first cache line.

16. The system of claim 11 , wherein there is one portio

Assignees

• Intel Corp

Inventors

• Li Yanru
• Kuo Chia-Hung
• Taha Ali

Classifications

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0868 Primary

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/0853

  Cache with multiport tag or data arrays · CPC title